Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
937395 |
0 |
0 |
T1 |
3095891 |
2133 |
0 |
0 |
T2 |
2652192 |
11591 |
0 |
0 |
T3 |
3548072 |
9836 |
0 |
0 |
T4 |
17779 |
0 |
0 |
0 |
T8 |
0 |
436 |
0 |
0 |
T9 |
0 |
96 |
0 |
0 |
T10 |
0 |
6167 |
0 |
0 |
T11 |
0 |
1966 |
0 |
0 |
T12 |
0 |
988 |
0 |
0 |
T15 |
90502 |
50 |
0 |
0 |
T16 |
11722 |
0 |
0 |
0 |
T17 |
33706 |
0 |
0 |
0 |
T18 |
8195 |
0 |
0 |
0 |
T19 |
8244 |
0 |
0 |
0 |
T20 |
17852 |
0 |
0 |
0 |
T21 |
0 |
872 |
0 |
0 |
T22 |
0 |
274 |
0 |
0 |
T44 |
11709 |
2 |
0 |
0 |
T45 |
11648 |
2 |
0 |
0 |
T47 |
13014 |
3 |
0 |
0 |
T48 |
6468 |
1 |
0 |
0 |
T49 |
18622 |
2 |
0 |
0 |
T103 |
15610 |
1 |
0 |
0 |
T104 |
12398 |
1 |
0 |
0 |
T105 |
7264 |
1 |
0 |
0 |
T106 |
13487 |
3 |
0 |
0 |
T107 |
7551 |
1 |
0 |
0 |
T108 |
4506 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
935058 |
0 |
0 |
T1 |
793775 |
2133 |
0 |
0 |
T2 |
3547616 |
11591 |
0 |
0 |
T3 |
1093564 |
9836 |
0 |
0 |
T4 |
5762 |
0 |
0 |
0 |
T8 |
0 |
436 |
0 |
0 |
T9 |
0 |
96 |
0 |
0 |
T10 |
0 |
6167 |
0 |
0 |
T11 |
0 |
1966 |
0 |
0 |
T12 |
0 |
988 |
0 |
0 |
T15 |
51762 |
50 |
0 |
0 |
T16 |
7027 |
0 |
0 |
0 |
T17 |
10852 |
0 |
0 |
0 |
T18 |
4767 |
0 |
0 |
0 |
T19 |
4814 |
0 |
0 |
0 |
T20 |
5391 |
0 |
0 |
0 |
T21 |
0 |
872 |
0 |
0 |
T22 |
0 |
274 |
0 |
0 |
T44 |
4912 |
2 |
0 |
0 |
T45 |
9672 |
2 |
0 |
0 |
T47 |
23824 |
3 |
0 |
0 |
T48 |
11768 |
1 |
0 |
0 |
T49 |
7268 |
2 |
0 |
0 |
T103 |
8956 |
1 |
0 |
0 |
T104 |
5476 |
1 |
0 |
0 |
T105 |
10338 |
1 |
0 |
0 |
T106 |
12607 |
3 |
0 |
0 |
T107 |
6811 |
1 |
0 |
0 |
T108 |
3729 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
325539763 |
25238 |
0 |
0 |
T1 |
750308 |
134 |
0 |
0 |
T2 |
105642 |
591 |
0 |
0 |
T3 |
896856 |
550 |
0 |
0 |
T4 |
4440 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
23419 |
10 |
0 |
0 |
T16 |
2464 |
0 |
0 |
0 |
T17 |
7923 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
4492 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
25238 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
591 |
0 |
0 |
T3 |
125899 |
550 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
10 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
325539763 |
31107 |
0 |
0 |
T1 |
750308 |
134 |
0 |
0 |
T2 |
105642 |
602 |
0 |
0 |
T3 |
896856 |
554 |
0 |
0 |
T4 |
4440 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
23419 |
20 |
0 |
0 |
T16 |
2464 |
0 |
0 |
0 |
T17 |
7923 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
4492 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31121 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31092 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
325539763 |
31108 |
0 |
0 |
T1 |
750308 |
134 |
0 |
0 |
T2 |
105642 |
602 |
0 |
0 |
T3 |
896856 |
554 |
0 |
0 |
T4 |
4440 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
23419 |
20 |
0 |
0 |
T16 |
2464 |
0 |
0 |
0 |
T17 |
7923 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
4492 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
161860189 |
25238 |
0 |
0 |
T1 |
375431 |
134 |
0 |
0 |
T2 |
528148 |
591 |
0 |
0 |
T3 |
448418 |
550 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
5644 |
10 |
0 |
0 |
T16 |
1179 |
0 |
0 |
0 |
T17 |
4420 |
0 |
0 |
0 |
T18 |
859 |
0 |
0 |
0 |
T19 |
854 |
0 |
0 |
0 |
T20 |
2213 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
25238 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
591 |
0 |
0 |
T3 |
125899 |
550 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
10 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
161860189 |
31259 |
0 |
0 |
T1 |
375431 |
134 |
0 |
0 |
T2 |
528148 |
602 |
0 |
0 |
T3 |
448418 |
554 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
5644 |
20 |
0 |
0 |
T16 |
1179 |
0 |
0 |
0 |
T17 |
4420 |
0 |
0 |
0 |
T18 |
859 |
0 |
0 |
0 |
T19 |
854 |
0 |
0 |
0 |
T20 |
2213 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31283 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31251 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
161860189 |
31263 |
0 |
0 |
T1 |
375431 |
134 |
0 |
0 |
T2 |
528148 |
602 |
0 |
0 |
T3 |
448418 |
554 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
5644 |
20 |
0 |
0 |
T16 |
1179 |
0 |
0 |
0 |
T17 |
4420 |
0 |
0 |
0 |
T18 |
859 |
0 |
0 |
0 |
T19 |
854 |
0 |
0 |
0 |
T20 |
2213 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80929489 |
25238 |
0 |
0 |
T1 |
187715 |
134 |
0 |
0 |
T2 |
264073 |
591 |
0 |
0 |
T3 |
224208 |
550 |
0 |
0 |
T4 |
1080 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
2822 |
10 |
0 |
0 |
T16 |
589 |
0 |
0 |
0 |
T17 |
2208 |
0 |
0 |
0 |
T18 |
428 |
0 |
0 |
0 |
T19 |
426 |
0 |
0 |
0 |
T20 |
1107 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
25238 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
591 |
0 |
0 |
T3 |
125899 |
550 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
10 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80929489 |
31162 |
0 |
0 |
T1 |
187715 |
134 |
0 |
0 |
T2 |
264073 |
602 |
0 |
0 |
T3 |
224208 |
554 |
0 |
0 |
T4 |
1080 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
2822 |
20 |
0 |
0 |
T16 |
589 |
0 |
0 |
0 |
T17 |
2208 |
0 |
0 |
0 |
T18 |
428 |
0 |
0 |
0 |
T19 |
426 |
0 |
0 |
0 |
T20 |
1107 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31201 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31153 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80929489 |
31164 |
0 |
0 |
T1 |
187715 |
134 |
0 |
0 |
T2 |
264073 |
602 |
0 |
0 |
T3 |
224208 |
554 |
0 |
0 |
T4 |
1080 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
2822 |
20 |
0 |
0 |
T16 |
589 |
0 |
0 |
0 |
T17 |
2208 |
0 |
0 |
0 |
T18 |
428 |
0 |
0 |
0 |
T19 |
426 |
0 |
0 |
0 |
T20 |
1107 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349717531 |
25238 |
0 |
0 |
T1 |
829595 |
134 |
0 |
0 |
T2 |
112927 |
591 |
0 |
0 |
T3 |
955855 |
550 |
0 |
0 |
T4 |
4624 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
24396 |
10 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
8253 |
0 |
0 |
0 |
T18 |
1778 |
0 |
0 |
0 |
T19 |
1800 |
0 |
0 |
0 |
T20 |
4679 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
25238 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
591 |
0 |
0 |
T3 |
125899 |
550 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
10 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349717531 |
31168 |
0 |
0 |
T1 |
829595 |
134 |
0 |
0 |
T2 |
112927 |
602 |
0 |
0 |
T3 |
955855 |
554 |
0 |
0 |
T4 |
4624 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
24396 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
8253 |
0 |
0 |
0 |
T18 |
1778 |
0 |
0 |
0 |
T19 |
1800 |
0 |
0 |
0 |
T20 |
4679 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31184 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31152 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349717531 |
31174 |
0 |
0 |
T1 |
829595 |
134 |
0 |
0 |
T2 |
112927 |
602 |
0 |
0 |
T3 |
955855 |
554 |
0 |
0 |
T4 |
4624 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
24396 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
8253 |
0 |
0 |
0 |
T18 |
1778 |
0 |
0 |
0 |
T19 |
1800 |
0 |
0 |
0 |
T20 |
4679 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167847880 |
24765 |
0 |
0 |
T1 |
401092 |
134 |
0 |
0 |
T2 |
544653 |
591 |
0 |
0 |
T3 |
460545 |
550 |
0 |
0 |
T4 |
2219 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
11709 |
5 |
0 |
0 |
T16 |
1231 |
0 |
0 |
0 |
T17 |
3962 |
0 |
0 |
0 |
T18 |
853 |
0 |
0 |
0 |
T19 |
864 |
0 |
0 |
0 |
T20 |
2245 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
25238 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
591 |
0 |
0 |
T3 |
125899 |
550 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
340 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
10 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167847880 |
31049 |
0 |
0 |
T1 |
401092 |
134 |
0 |
0 |
T2 |
544653 |
602 |
0 |
0 |
T3 |
460545 |
554 |
0 |
0 |
T4 |
2219 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
11709 |
15 |
0 |
0 |
T16 |
1231 |
0 |
0 |
0 |
T17 |
3962 |
0 |
0 |
0 |
T18 |
853 |
0 |
0 |
0 |
T19 |
864 |
0 |
0 |
0 |
T20 |
2245 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31288 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
20 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
30912 |
0 |
0 |
T1 |
201980 |
134 |
0 |
0 |
T2 |
585106 |
602 |
0 |
0 |
T3 |
125899 |
554 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
22933 |
15 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167847880 |
31081 |
0 |
0 |
T1 |
401092 |
134 |
0 |
0 |
T2 |
544653 |
602 |
0 |
0 |
T3 |
460545 |
554 |
0 |
0 |
T4 |
2219 |
0 |
0 |
0 |
T8 |
0 |
32 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
345 |
0 |
0 |
T11 |
0 |
130 |
0 |
0 |
T15 |
11709 |
15 |
0 |
0 |
T16 |
1231 |
0 |
0 |
0 |
T17 |
3962 |
0 |
0 |
0 |
T18 |
853 |
0 |
0 |
0 |
T19 |
864 |
0 |
0 |
0 |
T20 |
2245 |
0 |
0 |
0 |
T21 |
0 |
34 |
0 |
0 |
T22 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T46,T109,T110 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T46,T109,T110 |
1 | 1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
33 |
0 |
0 |
T44 |
11709 |
3 |
0 |
0 |
T45 |
5824 |
1 |
0 |
0 |
T46 |
15092 |
2 |
0 |
0 |
T48 |
3234 |
1 |
0 |
0 |
T49 |
9311 |
2 |
0 |
0 |
T103 |
7805 |
1 |
0 |
0 |
T104 |
6199 |
1 |
0 |
0 |
T106 |
13487 |
1 |
0 |
0 |
T109 |
6342 |
2 |
0 |
0 |
T111 |
6222 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
325539763 |
33 |
0 |
0 |
T44 |
11353 |
3 |
0 |
0 |
T45 |
11183 |
1 |
0 |
0 |
T46 |
30825 |
2 |
0 |
0 |
T48 |
12420 |
1 |
0 |
0 |
T49 |
9028 |
2 |
0 |
0 |
T103 |
10263 |
1 |
0 |
0 |
T104 |
6134 |
1 |
0 |
0 |
T106 |
26422 |
1 |
0 |
0 |
T109 |
12176 |
2 |
0 |
0 |
T111 |
23893 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T46,T109,T112 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T46,T109,T112 |
1 | 1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
30 |
0 |
0 |
T44 |
11709 |
1 |
0 |
0 |
T45 |
5824 |
1 |
0 |
0 |
T46 |
15092 |
3 |
0 |
0 |
T49 |
9311 |
1 |
0 |
0 |
T103 |
7805 |
1 |
0 |
0 |
T104 |
6199 |
1 |
0 |
0 |
T106 |
13487 |
1 |
0 |
0 |
T107 |
7551 |
2 |
0 |
0 |
T109 |
6342 |
2 |
0 |
0 |
T111 |
6222 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
325539763 |
30 |
0 |
0 |
T44 |
11353 |
1 |
0 |
0 |
T45 |
11183 |
1 |
0 |
0 |
T46 |
30825 |
3 |
0 |
0 |
T49 |
9028 |
1 |
0 |
0 |
T103 |
10263 |
1 |
0 |
0 |
T104 |
6134 |
1 |
0 |
0 |
T106 |
26422 |
1 |
0 |
0 |
T107 |
15102 |
2 |
0 |
0 |
T109 |
12176 |
2 |
0 |
0 |
T111 |
23893 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T48 |
1 | 0 | Covered | T44,T45,T48 |
1 | 1 | Covered | T45,T49,T47 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T48 |
1 | 0 | Covered | T45,T49,T47 |
1 | 1 | Covered | T44,T45,T48 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
45 |
0 |
0 |
T44 |
11709 |
2 |
0 |
0 |
T45 |
5824 |
2 |
0 |
0 |
T47 |
6507 |
3 |
0 |
0 |
T48 |
3234 |
1 |
0 |
0 |
T49 |
9311 |
2 |
0 |
0 |
T103 |
7805 |
1 |
0 |
0 |
T104 |
6199 |
1 |
0 |
0 |
T105 |
3632 |
1 |
0 |
0 |
T106 |
13487 |
3 |
0 |
0 |
T107 |
7551 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
161860189 |
45 |
0 |
0 |
T44 |
4912 |
2 |
0 |
0 |
T45 |
4836 |
2 |
0 |
0 |
T47 |
11912 |
3 |
0 |
0 |
T48 |
5884 |
1 |
0 |
0 |
T49 |
3634 |
2 |
0 |
0 |
T103 |
4478 |
1 |
0 |
0 |
T104 |
2738 |
1 |
0 |
0 |
T105 |
5169 |
1 |
0 |
0 |
T106 |
12607 |
3 |
0 |
0 |
T107 |
6811 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T45,T48,T49 |
1 | 1 | Covered | T49,T47,T105 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T49,T47,T105 |
1 | 1 | Covered | T45,T48,T49 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
44 |
0 |
0 |
T45 |
5824 |
1 |
0 |
0 |
T47 |
6507 |
4 |
0 |
0 |
T48 |
3234 |
1 |
0 |
0 |
T49 |
9311 |
2 |
0 |
0 |
T103 |
7805 |
1 |
0 |
0 |
T104 |
6199 |
1 |
0 |
0 |
T105 |
3632 |
2 |
0 |
0 |
T108 |
4506 |
1 |
0 |
0 |
T109 |
6342 |
2 |
0 |
0 |
T113 |
3034 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
161860189 |
44 |
0 |
0 |
T45 |
4836 |
1 |
0 |
0 |
T47 |
11912 |
4 |
0 |
0 |
T48 |
5884 |
1 |
0 |
0 |
T49 |
3634 |
2 |
0 |
0 |
T103 |
4478 |
1 |
0 |
0 |
T104 |
2738 |
1 |
0 |
0 |
T105 |
5169 |
2 |
0 |
0 |
T108 |
3729 |
1 |
0 |
0 |
T109 |
5570 |
2 |
0 |
0 |
T113 |
5316 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T47,T50 |
1 | 0 | Covered | T45,T47,T50 |
1 | 1 | Covered | T45,T114,T115 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T47,T50 |
1 | 0 | Covered | T45,T114,T115 |
1 | 1 | Covered | T45,T47,T50 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
27 |
0 |
0 |
T45 |
5824 |
2 |
0 |
0 |
T47 |
6507 |
2 |
0 |
0 |
T50 |
14919 |
2 |
0 |
0 |
T103 |
7805 |
1 |
0 |
0 |
T106 |
13487 |
1 |
0 |
0 |
T107 |
7551 |
1 |
0 |
0 |
T109 |
6342 |
1 |
0 |
0 |
T111 |
6222 |
1 |
0 |
0 |
T113 |
3034 |
1 |
0 |
0 |
T116 |
6867 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80929489 |
27 |
0 |
0 |
T45 |
2418 |
2 |
0 |
0 |
T47 |
5954 |
2 |
0 |
0 |
T50 |
3338 |
2 |
0 |
0 |
T103 |
2242 |
1 |
0 |
0 |
T106 |
6304 |
1 |
0 |
0 |
T107 |
3405 |
1 |
0 |
0 |
T109 |
2785 |
1 |
0 |
0 |
T111 |
5548 |
1 |
0 |
0 |
T113 |
2657 |
1 |
0 |
0 |
T116 |
2831 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T49,T47 |
1 | 0 | Covered | T45,T49,T47 |
1 | 1 | Covered | T47,T50,T114 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T49,T47 |
1 | 0 | Covered | T47,T50,T114 |
1 | 1 | Covered | T45,T49,T47 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31 |
0 |
0 |
T45 |
5824 |
1 |
0 |
0 |
T47 |
6507 |
2 |
0 |
0 |
T49 |
9311 |
1 |
0 |
0 |
T50 |
14919 |
3 |
0 |
0 |
T103 |
7805 |
2 |
0 |
0 |
T109 |
6342 |
2 |
0 |
0 |
T111 |
6222 |
2 |
0 |
0 |
T113 |
3034 |
1 |
0 |
0 |
T117 |
15169 |
1 |
0 |
0 |
T118 |
10585 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80929489 |
31 |
0 |
0 |
T45 |
2418 |
1 |
0 |
0 |
T47 |
5954 |
2 |
0 |
0 |
T49 |
1821 |
1 |
0 |
0 |
T50 |
3338 |
3 |
0 |
0 |
T103 |
2242 |
2 |
0 |
0 |
T109 |
2785 |
2 |
0 |
0 |
T111 |
5548 |
2 |
0 |
0 |
T113 |
2657 |
1 |
0 |
0 |
T117 |
3359 |
1 |
0 |
0 |
T118 |
2127 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T46,T49 |
1 | 0 | Covered | T45,T46,T49 |
1 | 1 | Covered | T119,T120 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T46,T49 |
1 | 0 | Covered | T119,T120 |
1 | 1 | Covered | T45,T46,T49 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
25 |
0 |
0 |
T45 |
5824 |
1 |
0 |
0 |
T46 |
15092 |
2 |
0 |
0 |
T47 |
6507 |
1 |
0 |
0 |
T49 |
9311 |
1 |
0 |
0 |
T103 |
7805 |
1 |
0 |
0 |
T104 |
6199 |
1 |
0 |
0 |
T105 |
3632 |
1 |
0 |
0 |
T107 |
7551 |
2 |
0 |
0 |
T108 |
4506 |
2 |
0 |
0 |
T119 |
11721 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349717531 |
25 |
0 |
0 |
T45 |
11649 |
1 |
0 |
0 |
T46 |
32111 |
2 |
0 |
0 |
T47 |
26031 |
1 |
0 |
0 |
T49 |
9405 |
1 |
0 |
0 |
T103 |
10692 |
1 |
0 |
0 |
T104 |
6390 |
1 |
0 |
0 |
T105 |
11720 |
1 |
0 |
0 |
T107 |
15732 |
2 |
0 |
0 |
T108 |
9387 |
2 |
0 |
0 |
T119 |
11839 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T119,T121,T122 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T119,T121,T122 |
1 | 1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
34 |
0 |
0 |
T44 |
11709 |
1 |
0 |
0 |
T45 |
5824 |
1 |
0 |
0 |
T46 |
15092 |
1 |
0 |
0 |
T49 |
9311 |
1 |
0 |
0 |
T104 |
6199 |
1 |
0 |
0 |
T105 |
3632 |
1 |
0 |
0 |
T113 |
3034 |
1 |
0 |
0 |
T118 |
10585 |
2 |
0 |
0 |
T119 |
11721 |
5 |
0 |
0 |
T121 |
2658 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349717531 |
34 |
0 |
0 |
T44 |
11827 |
1 |
0 |
0 |
T45 |
11649 |
1 |
0 |
0 |
T46 |
32111 |
1 |
0 |
0 |
T49 |
9405 |
1 |
0 |
0 |
T104 |
6390 |
1 |
0 |
0 |
T105 |
11720 |
1 |
0 |
0 |
T113 |
12140 |
1 |
0 |
0 |
T118 |
10801 |
2 |
0 |
0 |
T119 |
11839 |
5 |
0 |
0 |
T121 |
12084 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T49,T50 |
1 | 0 | Covered | T45,T49,T50 |
1 | 1 | Covered | T49,T119,T118 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T45,T49,T50 |
1 | 0 | Covered | T49,T119,T118 |
1 | 1 | Covered | T45,T49,T50 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
29 |
0 |
0 |
T45 |
5824 |
1 |
0 |
0 |
T49 |
9311 |
2 |
0 |
0 |
T50 |
14919 |
2 |
0 |
0 |
T108 |
4506 |
1 |
0 |
0 |
T111 |
6222 |
1 |
0 |
0 |
T113 |
3034 |
1 |
0 |
0 |
T117 |
15169 |
1 |
0 |
0 |
T118 |
10585 |
3 |
0 |
0 |
T119 |
11721 |
2 |
0 |
0 |
T123 |
6159 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167847880 |
29 |
0 |
0 |
T45 |
5592 |
1 |
0 |
0 |
T49 |
4514 |
2 |
0 |
0 |
T50 |
7460 |
2 |
0 |
0 |
T108 |
4506 |
1 |
0 |
0 |
T111 |
11947 |
1 |
0 |
0 |
T113 |
5827 |
1 |
0 |
0 |
T117 |
7664 |
1 |
0 |
0 |
T118 |
5185 |
3 |
0 |
0 |
T119 |
5683 |
2 |
0 |
0 |
T123 |
3080 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T49,T47 |
1 | 0 | Covered | T44,T49,T47 |
1 | 1 | Covered | T49,T119,T118 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T49,T47 |
1 | 0 | Covered | T49,T119,T118 |
1 | 1 | Covered | T44,T49,T47 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160591745 |
31 |
0 |
0 |
T44 |
11709 |
2 |
0 |
0 |
T47 |
6507 |
2 |
0 |
0 |
T49 |
9311 |
2 |
0 |
0 |
T50 |
14919 |
3 |
0 |
0 |
T111 |
6222 |
1 |
0 |
0 |
T113 |
3034 |
1 |
0 |
0 |
T114 |
11105 |
2 |
0 |
0 |
T117 |
15169 |
1 |
0 |
0 |
T118 |
10585 |
2 |
0 |
0 |
T119 |
11721 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167847880 |
31 |
0 |
0 |
T44 |
5677 |
2 |
0 |
0 |
T47 |
12495 |
2 |
0 |
0 |
T49 |
4514 |
2 |
0 |
0 |
T50 |
7460 |
3 |
0 |
0 |
T111 |
11947 |
1 |
0 |
0 |
T113 |
5827 |
1 |
0 |
0 |
T114 |
6923 |
2 |
0 |
0 |
T117 |
7664 |
1 |
0 |
0 |
T118 |
5185 |
2 |
0 |
0 |
T119 |
5683 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
323122392 |
92986 |
0 |
0 |
T1 |
750308 |
409 |
0 |
0 |
T2 |
105642 |
2323 |
0 |
0 |
T3 |
896856 |
1944 |
0 |
0 |
T4 |
4440 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1193 |
0 |
0 |
T11 |
0 |
388 |
0 |
0 |
T12 |
0 |
244 |
0 |
0 |
T15 |
23419 |
0 |
0 |
0 |
T16 |
2464 |
0 |
0 |
0 |
T17 |
7923 |
0 |
0 |
0 |
T18 |
1706 |
0 |
0 |
0 |
T19 |
1728 |
0 |
0 |
0 |
T20 |
4492 |
0 |
0 |
0 |
T21 |
0 |
189 |
0 |
0 |
T22 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11393135 |
92366 |
0 |
0 |
T1 |
3572 |
409 |
0 |
0 |
T2 |
462170 |
2323 |
0 |
0 |
T3 |
98229 |
1944 |
0 |
0 |
T4 |
323 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1193 |
0 |
0 |
T11 |
0 |
388 |
0 |
0 |
T12 |
0 |
244 |
0 |
0 |
T15 |
63 |
0 |
0 |
0 |
T16 |
179 |
0 |
0 |
0 |
T17 |
577 |
0 |
0 |
0 |
T18 |
124 |
0 |
0 |
0 |
T19 |
126 |
0 |
0 |
0 |
T20 |
327 |
0 |
0 |
0 |
T21 |
0 |
189 |
0 |
0 |
T22 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160695878 |
92601 |
0 |
0 |
T1 |
375431 |
409 |
0 |
0 |
T2 |
528148 |
2312 |
0 |
0 |
T3 |
448418 |
1940 |
0 |
0 |
T4 |
2160 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1193 |
0 |
0 |
T11 |
0 |
388 |
0 |
0 |
T12 |
0 |
244 |
0 |
0 |
T15 |
5644 |
0 |
0 |
0 |
T16 |
1179 |
0 |
0 |
0 |
T17 |
4420 |
0 |
0 |
0 |
T18 |
859 |
0 |
0 |
0 |
T19 |
854 |
0 |
0 |
0 |
T20 |
2213 |
0 |
0 |
0 |
T21 |
0 |
189 |
0 |
0 |
T22 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11393135 |
91981 |
0 |
0 |
T1 |
3572 |
409 |
0 |
0 |
T2 |
462170 |
2312 |
0 |
0 |
T3 |
98229 |
1940 |
0 |
0 |
T4 |
323 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1193 |
0 |
0 |
T11 |
0 |
388 |
0 |
0 |
T12 |
0 |
244 |
0 |
0 |
T15 |
63 |
0 |
0 |
0 |
T16 |
179 |
0 |
0 |
0 |
T17 |
577 |
0 |
0 |
0 |
T18 |
124 |
0 |
0 |
0 |
T19 |
126 |
0 |
0 |
0 |
T20 |
327 |
0 |
0 |
0 |
T21 |
0 |
189 |
0 |
0 |
T22 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80347326 |
91764 |
0 |
0 |
T1 |
187715 |
409 |
0 |
0 |
T2 |
264073 |
2300 |
0 |
0 |
T3 |
224208 |
1935 |
0 |
0 |
T4 |
1080 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1190 |
0 |
0 |
T11 |
0 |
388 |
0 |
0 |
T12 |
0 |
244 |
0 |
0 |
T15 |
2822 |
0 |
0 |
0 |
T16 |
589 |
0 |
0 |
0 |
T17 |
2208 |
0 |
0 |
0 |
T18 |
428 |
0 |
0 |
0 |
T19 |
426 |
0 |
0 |
0 |
T20 |
1107 |
0 |
0 |
0 |
T21 |
0 |
189 |
0 |
0 |
T22 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11393135 |
91152 |
0 |
0 |
T1 |
3572 |
409 |
0 |
0 |
T2 |
462170 |
2300 |
0 |
0 |
T3 |
98229 |
1935 |
0 |
0 |
T4 |
323 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1190 |
0 |
0 |
T11 |
0 |
388 |
0 |
0 |
T12 |
0 |
244 |
0 |
0 |
T15 |
63 |
0 |
0 |
0 |
T16 |
179 |
0 |
0 |
0 |
T17 |
577 |
0 |
0 |
0 |
T18 |
124 |
0 |
0 |
0 |
T19 |
126 |
0 |
0 |
0 |
T20 |
327 |
0 |
0 |
0 |
T21 |
0 |
189 |
0 |
0 |
T22 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
111987 |
0 |
0 |
T1 |
829595 |
504 |
0 |
0 |
T2 |
112927 |
2861 |
0 |
0 |
T3 |
955855 |
2359 |
0 |
0 |
T4 |
4624 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1561 |
0 |
0 |
T11 |
0 |
412 |
0 |
0 |
T12 |
0 |
256 |
0 |
0 |
T15 |
24396 |
0 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
8253 |
0 |
0 |
0 |
T18 |
1778 |
0 |
0 |
0 |
T19 |
1800 |
0 |
0 |
0 |
T20 |
4679 |
0 |
0 |
0 |
T21 |
0 |
203 |
0 |
0 |
T22 |
0 |
85 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11376123 |
111614 |
0 |
0 |
T1 |
3668 |
504 |
0 |
0 |
T2 |
462746 |
2861 |
0 |
0 |
T3 |
98661 |
2359 |
0 |
0 |
T4 |
323 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1561 |
0 |
0 |
T11 |
0 |
412 |
0 |
0 |
T12 |
0 |
256 |
0 |
0 |
T15 |
63 |
0 |
0 |
0 |
T16 |
179 |
0 |
0 |
0 |
T17 |
577 |
0 |
0 |
0 |
T18 |
124 |
0 |
0 |
0 |
T19 |
126 |
0 |
0 |
0 |
T20 |
327 |
0 |
0 |
0 |
T21 |
0 |
203 |
0 |
0 |
T22 |
0 |
85 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166639179 |
110706 |
0 |
0 |
T1 |
401092 |
505 |
0 |
0 |
T2 |
544653 |
2961 |
0 |
0 |
T3 |
460545 |
2407 |
0 |
0 |
T4 |
2219 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1499 |
0 |
0 |
T11 |
0 |
388 |
0 |
0 |
T12 |
0 |
268 |
0 |
0 |
T15 |
11709 |
0 |
0 |
0 |
T16 |
1231 |
0 |
0 |
0 |
T17 |
3962 |
0 |
0 |
0 |
T18 |
853 |
0 |
0 |
0 |
T19 |
864 |
0 |
0 |
0 |
T20 |
2245 |
0 |
0 |
0 |
T21 |
0 |
232 |
0 |
0 |
T22 |
0 |
93 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11327059 |
109559 |
0 |
0 |
T1 |
3680 |
505 |
0 |
0 |
T2 |
462854 |
2961 |
0 |
0 |
T3 |
98733 |
2407 |
0 |
0 |
T4 |
323 |
0 |
0 |
0 |
T8 |
0 |
85 |
0 |
0 |
T9 |
0 |
18 |
0 |
0 |
T10 |
0 |
1499 |
0 |
0 |
T11 |
0 |
388 |
0 |
0 |
T12 |
0 |
268 |
0 |
0 |
T15 |
63 |
0 |
0 |
0 |
T16 |
179 |
0 |
0 |
0 |
T17 |
577 |
0 |
0 |
0 |
T18 |
124 |
0 |
0 |
0 |
T19 |
126 |
0 |
0 |
0 |
T20 |
327 |
0 |
0 |
0 |
T21 |
0 |
232 |
0 |
0 |
T22 |
0 |
93 |
0 |
0 |