Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160591745	5201155	0	0
clk_enables_rd_A	160591745	44947	0	0
clk_hints_rd_A	160591745	39894	0	0
extclk_ctrl_rd_A	160591745	50076	0	0
extclk_ctrl_regwen_rd_A	160591745	37230	0	0
jitter_enable_rd_A	160591745	56829	0	0
jitter_regwen_rd_A	160591745	42583	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160591745	5201155	0	0
T2	585106	184625	0	0
T3	125899	58172	0	0
T4	1155	0	0	0
T10	0	69178	0	0
T14	0	154113	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0
T23	0	143750	0	0
T24	0	72269	0	0
T51	0	76005	0	0
T52	0	138383	0	0
T53	0	30267	0	0
T54	0	126679	0	0
T55	853	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160591745	44947	0	0
T2	585106	3571	0	0
T3	125899	0	0	0
T4	1155	0	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0
T21	0	11	0	0
T29	0	9	0	0
T52	0	5562	0	0
T53	0	735	0	0
T55	853	0	0	0
T95	0	6	0	0
T124	0	9	0	0
T125	0	11	0	0
T126	0	1857	0	0
T127	0	8	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160591745	39894	0	0
T2	585106	3184	0	0
T3	125899	0	0	0
T4	1155	0	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0
T21	0	18	0	0
T52	0	4899	0	0
T53	0	599	0	0
T55	853	0	0	0
T95	0	1	0	0
T125	0	5	0	0
T126	0	1661	0	0
T128	0	8	0	0
T129	0	2	0	0
T130	0	8	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160591745	50076	0	0
T2	585106	3766	0	0
T3	125899	0	0	0
T4	1155	0	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	66	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0
T21	0	8	0	0
T38	0	27	0	0
T52	0	5864	0	0
T55	853	0	0	0
T57	0	4	0	0
T131	0	8	0	0
T132	0	15	0	0
T133	0	10	0	0
T134	0	67	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160591745	37230	0	0
T2	585106	3224	0	0
T3	125899	0	0	0
T4	1155	0	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0
T52	0	4858	0	0
T53	0	491	0	0
T55	853	0	0	0
T126	0	1437	0	0
T135	0	14	0	0
T136	0	31	0	0
T137	0	2007	0	0
T138	0	90	0	0
T139	0	40	0	0
T140	0	3838	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160591745	56829	0	0
T2	585106	3832	0	0
T3	125899	0	0	0
T4	1155	0	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0
T21	0	320	0	0
T52	0	6999	0	0
T53	0	889	0	0
T55	853	0	0	0
T95	0	172	0	0
T96	0	70	0	0
T124	0	58	0	0
T128	0	86	0	0
T129	0	110	0	0
T130	0	98	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160591745	42583	0	0
T2	585106	3719	0	0
T3	125899	0	0	0
T4	1155	0	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0
T52	0	5524	0	0
T53	0	627	0	0
T55	853	0	0	0
T126	0	1746	0	0
T137	0	2385	0	0
T140	0	4245	0	0
T141	0	3547	0	0
T142	0	2450	0	0
T143	0	3754	0	0
T144	0	853	0	0