Module Definition
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Module : prim_sync_reqack
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout 87.50 100.00 100.00 100.00 50.00
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_io_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_io_div2_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_io_div4_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_main_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00
tb.dut.u_usb_meas.u_err_sync 93.75 100.00 75.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_clk_timeout_chk.u_timeout_ref_to_clk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.61 90.00 76.19 78.26 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.61 90.00 76.19 78.26 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
79.17 94.00 85.71 86.96 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.61 90.00 76.19 78.26 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.61 90.00 76.19 78.26 50.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 2147483647 12686092 0 0
SyncReqAckHoldReq 2147483647 140003 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 12686092 0 0
T1 4563941 3374 0 0
T2 7406503 406875 0 0
T3 4244872 87546 0 0
T4 26073 272 0 0
T8 0 58 0 0
T9 0 13 0 0
T10 0 517 0 0
T11 0 220 0 0
T12 0 21 0 0
T13 0 22 0 0
T14 0 556 0 0
T15 297320 26 0 0
T16 33689 150 0 0
T17 47386 507 0 0
T18 22684 98 0 0
T19 22952 102 0 0
T20 24086 274 0 0
T21 0 38 0 0
T22 0 12 0 0
T23 0 84 0 0
T24 0 52 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 140003 0 0
T1 5088282 775 0 0
T2 3110886 3244 0 0
T3 5971764 3089 0 0
T4 29046 0 0 0
T8 0 188 0 0
T9 0 44 0 0
T10 0 1898 0 0
T11 0 784 0 0
T12 0 103 0 0
T13 0 26 0 0
T14 0 665 0 0
T15 135980 38 0 0
T16 16058 0 0 0
T17 53532 0 0 0
T18 11248 0 0 0
T19 11344 0 0 0
T20 29472 0 0 0
T21 0 174 0 0
T22 0 60 0 0
T23 0 106 0 0
T24 0 52 0 0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T4

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 323122392 2529800 0 0
SyncReqAckHoldReq 11435103 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 323122392 2529800 0 0
T1 750308 790 0 0
T2 105642 102645 0 0
T3 896856 21855 0 0
T4 4440 69 0 0
T15 23419 4 0 0
T16 2464 38 0 0
T17 7923 128 0 0
T18 1706 25 0 0
T19 1728 26 0 0
T20 4492 69 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 11435103 0 0 0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T4

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 160695878 2529691 0 0
SyncReqAckHoldReq 11435103 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 160695878 2529691 0 0
T1 375431 790 0 0
T2 528148 102644 0 0
T3 448418 21855 0 0
T4 2160 69 0 0
T15 5644 4 0 0
T16 1179 38 0 0
T17 4420 128 0 0
T18 859 25 0 0
T19 854 26 0 0
T20 2213 69 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 11435103 0 0 0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T4

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 80347326 2412850 0 0
SyncReqAckHoldReq 11435103 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 80347326 2412850 0 0
T1 187715 762 0 0
T2 264073 97984 0 0
T3 224208 21037 0 0
T4 1080 65 0 0
T15 2822 4 0 0
T16 589 36 0 0
T17 2208 123 0 0
T18 428 23 0 0
T19 426 24 0 0
T20 1107 67 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 11435103 0 0 0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T4

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 347199334 2533813 0 0
SyncReqAckHoldReq 11435103 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 347199334 2533813 0 0
T1 829595 808 0 0
T2 112927 102755 0 0
T3 955855 21938 0 0
T4 4624 69 0 0
T15 24396 4 0 0
T16 2566 38 0 0
T17 8253 128 0 0
T18 1778 25 0 0
T19 1800 26 0 0
T20 4679 69 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 11435103 0 0 0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T4

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T4
EVEN 0 - Covered T1,T2,T4
ODD - 1 Covered T1,T2,T4
ODD - 0 Covered T1,T2,T4


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 166639179 2533770 0 0
SyncReqAckHoldReq 11435103 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 166639179 2533770 0 0
T1 401092 809 0 0
T2 544653 102774 0 0
T3 460545 21953 0 0
T4 2219 69 0 0
T15 11709 4 0 0
T16 1231 38 0 0
T17 3962 128 0 0
T18 853 25 0 0
T19 864 26 0 0
T20 2245 69 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 11435103 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 160591745 26420 0 0
SyncReqAckHoldReq 325539763 25238 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 160591745 26420 0 0
T1 201980 145 0 0
T2 585106 615 0 0
T3 125899 578 0 0
T4 1155 0 0 0
T8 0 34 0 0
T9 0 9 0 0
T10 0 359 0 0
T11 0 137 0 0
T15 22933 10 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T21 0 34 0 0
T22 0 12 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 325539763 25238 0 0
T1 750308 134 0 0
T2 105642 591 0 0
T3 896856 550 0 0
T4 4440 0 0 0
T8 0 32 0 0
T9 0 8 0 0
T10 0 340 0 0
T11 0 130 0 0
T15 23419 10 0 0
T16 2464 0 0 0
T17 7923 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 4492 0 0 0
T21 0 34 0 0
T22 0 12 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 160591745 26420 0 0
SyncReqAckHoldReq 161860189 25235 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 160591745 26420 0 0
T1 201980 145 0 0
T2 585106 615 0 0
T3 125899 578 0 0
T4 1155 0 0 0
T8 0 34 0 0
T9 0 9 0 0
T10 0 359 0 0
T11 0 137 0 0
T15 22933 10 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T21 0 34 0 0
T22 0 12 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 161860189 25235 0 0
T1 375431 134 0 0
T2 528148 591 0 0
T3 448418 550 0 0
T4 2160 0 0 0
T8 0 32 0 0
T9 0 8 0 0
T10 0 340 0 0
T11 0 130 0 0
T15 5644 10 0 0
T16 1179 0 0 0
T17 4420 0 0 0
T18 859 0 0 0
T19 854 0 0 0
T20 2213 0 0 0
T21 0 34 0 0
T22 0 12 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 160591745 26420 0 0
SyncReqAckHoldReq 80929489 25170 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 160591745 26420 0 0
T1 201980 145 0 0
T2 585106 615 0 0
T3 125899 578 0 0
T4 1155 0 0 0
T8 0 34 0 0
T9 0 9 0 0
T10 0 359 0 0
T11 0 137 0 0
T15 22933 10 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T21 0 34 0 0
T22 0 12 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 80929489 25170 0 0
T1 187715 134 0 0
T2 264073 591 0 0
T3 224208 550 0 0
T4 1080 0 0 0
T8 0 32 0 0
T9 0 8 0 0
T10 0 340 0 0
T11 0 130 0 0
T15 2822 8 0 0
T16 589 0 0 0
T17 2208 0 0 0
T18 428 0 0 0
T19 426 0 0 0
T20 1107 0 0 0
T21 0 34 0 0
T22 0 12 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 160591745 26420 0 0
SyncReqAckHoldReq 349717531 25238 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 160591745 26420 0 0
T1 201980 145 0 0
T2 585106 615 0 0
T3 125899 578 0 0
T4 1155 0 0 0
T8 0 34 0 0
T9 0 9 0 0
T10 0 359 0 0
T11 0 137 0 0
T15 22933 10 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T21 0 34 0 0
T22 0 12 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 349717531 25238 0 0
T1 829595 134 0 0
T2 112927 591 0 0
T3 955855 550 0 0
T4 4624 0 0 0
T8 0 32 0 0
T9 0 8 0 0
T10 0 340 0 0
T11 0 130 0 0
T15 24396 10 0 0
T16 2566 0 0 0
T17 8253 0 0 0
T18 1778 0 0 0
T19 1800 0 0 0
T20 4679 0 0 0
T21 0 34 0 0
T22 0 12 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 160591745 25907 0 0
SyncReqAckHoldReq 167847880 24542 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 160591745 25907 0 0
T1 201980 145 0 0
T2 585106 615 0 0
T3 125899 578 0 0
T4 1155 0 0 0
T8 0 34 0 0
T9 0 9 0 0
T10 0 359 0 0
T11 0 137 0 0
T15 22933 5 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T21 0 34 0 0
T22 0 12 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 167847880 24542 0 0
T1 401092 134 0 0
T2 544653 591 0 0
T3 460545 550 0 0
T4 2219 0 0 0
T8 0 32 0 0
T9 0 8 0 0
T10 0 340 0 0
T11 0 130 0 0
T12 0 68 0 0
T15 11709 0 0 0
T16 1231 0 0 0
T17 3962 0 0 0
T18 853 0 0 0
T19 864 0 0 0
T20 2245 0 0 0
T21 0 34 0 0
T22 0 12 0 0

Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_io_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 159692791 2955 0 0
SyncReqAckHoldReq 323122392 2955 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 159692791 2955 0 0
T1 201980 11 0 0
T2 585106 47 0 0
T3 125899 90 0 0
T4 1155 0 0 0
T8 0 3 0 0
T10 0 71 0 0
T11 0 37 0 0
T12 0 11 0 0
T13 0 11 0 0
T14 0 169 0 0
T15 22933 0 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T23 0 17 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 323122392 2955 0 0
T1 750308 11 0 0
T2 105642 47 0 0
T3 896856 90 0 0
T4 4440 0 0 0
T8 0 3 0 0
T10 0 71 0 0
T11 0 37 0 0
T12 0 11 0 0
T13 0 11 0 0
T14 0 169 0 0
T15 23419 0 0 0
T16 2464 0 0 0
T17 7923 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 4492 0 0 0
T23 0 17 0 0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 159692791 3028 0 0
SyncReqAckHoldReq 160695878 3027 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 159692791 3028 0 0
T1 201980 37 0 0
T2 585106 68 0 0
T3 125899 50 0 0
T4 1155 0 0 0
T8 0 7 0 0
T9 0 4 0 0
T10 0 13 0 0
T11 0 17 0 0
T13 0 4 0 0
T14 0 114 0 0
T15 22933 0 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T23 0 13 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 160695878 3027 0 0
T1 375431 37 0 0
T2 528148 68 0 0
T3 448418 50 0 0
T4 2160 0 0 0
T8 0 7 0 0
T9 0 4 0 0
T10 0 13 0 0
T11 0 17 0 0
T13 0 4 0 0
T14 0 114 0 0
T15 5644 0 0 0
T16 1179 0 0 0
T17 4420 0 0 0
T18 859 0 0 0
T19 854 0 0 0
T20 2213 0 0 0
T23 0 13 0 0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 159692791 3034 0 0
SyncReqAckHoldReq 80347326 3034 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 159692791 3034 0 0
T1 201980 7 0 0
T2 585106 61 0 0
T3 125899 88 0 0
T4 1155 0 0 0
T8 0 4 0 0
T10 0 52 0 0
T11 0 13 0 0
T12 0 7 0 0
T14 0 185 0 0
T15 22933 0 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T23 0 54 0 0
T24 0 52 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 80347326 3034 0 0
T1 187715 7 0 0
T2 264073 61 0 0
T3 224208 88 0 0
T4 1080 0 0 0
T8 0 4 0 0
T10 0 52 0 0
T11 0 13 0 0
T12 0 7 0 0
T14 0 185 0 0
T15 2822 0 0 0
T16 589 0 0 0
T17 2208 0 0 0
T18 428 0 0 0
T19 426 0 0 0
T20 1107 0 0 0
T23 0 54 0 0
T24 0 52 0 0

Line Coverage for Instance : tb.dut.u_main_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_main_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_main_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_main_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 159692791 2707 0 0
SyncReqAckHoldReq 347199334 2707 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 159692791 2707 0 0
T1 201980 24 0 0
T2 585106 56 0 0
T3 125899 55 0 0
T4 1155 0 0 0
T8 0 10 0 0
T10 0 22 0 0
T11 0 16 0 0
T12 0 3 0 0
T13 0 7 0 0
T14 0 88 0 0
T15 22933 0 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T21 0 4 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 347199334 2707 0 0
T1 829595 24 0 0
T2 112927 56 0 0
T3 955855 55 0 0
T4 4624 0 0 0
T8 0 10 0 0
T10 0 22 0 0
T11 0 16 0 0
T12 0 3 0 0
T13 0 7 0 0
T14 0 88 0 0
T15 24396 0 0 0
T16 2566 0 0 0
T17 8253 0 0 0
T18 1778 0 0 0
T19 1800 0 0 0
T20 4679 0 0 0
T21 0 4 0 0

Line Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
TotalCoveredPercent
Conditions4375.00
Logical4375.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T2,T3
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


Assert Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 159692791 2857 0 0
SyncReqAckHoldReq 166639179 2857 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 159692791 2857 0 0
T1 201980 26 0 0
T2 585106 57 0 0
T3 125899 56 0 0
T4 1155 0 0 0
T8 0 4 0 0
T10 0 40 0 0
T11 0 51 0 0
T12 0 14 0 0
T13 0 4 0 0
T14 0 109 0 0
T15 22933 0 0 0
T16 2566 0 0 0
T17 2062 0 0 0
T18 1706 0 0 0
T19 1728 0 0 0
T20 935 0 0 0
T23 0 22 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 166639179 2857 0 0
T1 401092 26 0 0
T2 544653 57 0 0
T3 460545 56 0 0
T4 2219 0 0 0
T8 0 4 0 0
T10 0 40 0 0
T11 0 51 0 0
T12 0 14 0 0
T13 0 4 0 0
T14 0 109 0 0
T15 11709 0 0 0
T16 1231 0 0 0
T17 3962 0 0 0
T18 853 0 0 0
T19 864 0 0 0
T20 2245 0 0 0
T23 0 22 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%