Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	479078373	430	0	0
StatusRise_A	479078373	430	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479078373	430	0	0
T22	58917	0	0	0
T31	2838	4	0	0
T32	0	4	0	0
T33	0	10	0	0
T97	5652	0	0	0
T131	5724	0	0	0
T132	5124	0	0	0
T133	4374	0	0	0
T145	0	6	0	0
T146	0	15	0	0
T147	0	14	0	0
T148	0	5	0	0
T149	0	7	0	0
T150	0	7	0	0
T151	0	11	0	0
T152	3384	0	0	0
T153	7098	0	0	0
T154	6720	0	0	0
T155	3705	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479078373	430	0	0
T22	58917	0	0	0
T31	2838	4	0	0
T32	0	4	0	0
T33	0	10	0	0
T97	5652	0	0	0
T131	5724	0	0	0
T132	5124	0	0	0
T133	4374	0	0	0
T145	0	6	0	0
T146	0	15	0	0
T147	0	14	0	0
T148	0	5	0	0
T149	0	7	0	0
T150	0	7	0	0
T151	0	11	0	0
T152	3384	0	0	0
T153	7098	0	0	0
T154	6720	0	0	0
T155	3705	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	159692791	138	0	0
StatusRise_A	159692791	138	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	138	0	0
T22	19639	0	0	0
T31	946	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T97	1884	0	0	0
T131	1908	0	0	0
T132	1708	0	0	0
T133	1458	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	3	0	0
T151	0	3	0	0
T152	1128	0	0	0
T153	2366	0	0	0
T154	2240	0	0	0
T155	1235	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	138	0	0
T22	19639	0	0	0
T31	946	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T97	1884	0	0	0
T131	1908	0	0	0
T132	1708	0	0	0
T133	1458	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	3	0	0
T151	0	3	0	0
T152	1128	0	0	0
T153	2366	0	0	0
T154	2240	0	0	0
T155	1235	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	159692791	140	0	0
StatusRise_A	159692791	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	140	0	0
T22	19639	0	0	0
T31	946	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	1884	0	0	0
T131	1908	0	0	0
T132	1708	0	0	0
T133	1458	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0
T152	1128	0	0	0
T153	2366	0	0	0
T154	2240	0	0	0
T155	1235	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	140	0	0
T22	19639	0	0	0
T31	946	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	1884	0	0	0
T131	1908	0	0	0
T132	1708	0	0	0
T133	1458	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0
T152	1128	0	0	0
T153	2366	0	0	0
T154	2240	0	0	0
T155	1235	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	159692791	152	0	0
StatusRise_A	159692791	152	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	152	0	0
T22	19639	0	0	0
T31	946	2	0	0
T32	0	1	0	0
T33	0	4	0	0
T97	1884	0	0	0
T131	1908	0	0	0
T132	1708	0	0	0
T133	1458	0	0	0
T145	0	1	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T152	1128	0	0	0
T153	2366	0	0	0
T154	2240	0	0	0
T155	1235	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	152	0	0
T22	19639	0	0	0
T31	946	2	0	0
T32	0	1	0	0
T33	0	4	0	0
T97	1884	0	0	0
T131	1908	0	0	0
T132	1708	0	0	0
T133	1458	0	0	0
T145	0	1	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T152	1128	0	0	0
T153	2366	0	0	0
T154	2240	0	0	0
T155	1235	0	0	0