Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51780	0	0
CgEnOn_A	2147483647	42274	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51780	0	0
T1	5032926	32	0	0
T2	1894224	440	0	0
T3	5853447	288	0	0
T4	28395	7	0	0
T15	141178	18	0	0
T16	15727	9	0	0
T17	51525	3	0	0
T18	10958	3	0	0
T19	11072	3	0	0
T20	28773	3	0	0
T22	300523	0	0	0
T24	0	5	0	0
T31	19006	5	0	0
T32	0	10	0	0
T33	0	15	0	0
T56	0	10	0	0
T97	9661	0	0	0
T131	8814	0	0	0
T132	15604	0	0	0
T133	7912	0	0	0
T145	0	15	0	0
T146	0	20	0	0
T147	0	20	0	0
T148	0	10	0	0
T149	0	10	0	0
T150	0	5	0	0
T152	10593	0	0	0
T153	11484	0	0	0
T154	10863	0	0	0
T155	26024	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42274	0	0
T1	829595	11	0	0
T2	1010790	407	0	0
T3	2525337	273	0	0
T4	12304	4	0	0
T10	0	261	0	0
T11	0	122	0	0
T15	56281	0	0	0
T16	6798	0	0	0
T17	22804	0	0	0
T18	4771	0	0	0
T19	4808	0	0	0
T20	12491	0	0	0
T21	0	22	0	0
T22	117696	0	0	0
T24	0	4	0	0
T31	8989	8	0	0
T32	0	10	0	0
T33	0	15	0	0
T41	0	37	0	0
T55	5908	3	0	0
T96	0	4	0	0
T97	4473	0	0	0
T131	4083	0	0	0
T132	7293	0	0	0
T133	3657	0	0	0
T145	0	15	0	0
T146	0	20	0	0
T147	0	20	0	0
T148	0	10	0	0
T149	0	10	0	0
T150	0	5	0	0
T151	0	4	0	0
T152	4887	0	0	0
T153	5311	0	0	0
T154	5076	0	0	0
T155	12089	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	160695878	146	0	0
CgEnOn_A	160695878	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160695878	146	0	0
T22	26128	0	0	0
T24	0	1	0	0
T31	1992	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	985	0	0	0
T131	901	0	0	0
T132	1631	0	0	0
T133	804	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	1071	0	0	0
T153	1169	0	0	0
T154	1135	0	0	0
T155	2678	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160695878	146	0	0
T22	26128	0	0	0
T24	0	1	0	0
T31	1992	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	985	0	0	0
T131	901	0	0	0
T132	1631	0	0	0
T133	804	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	1071	0	0	0
T153	1169	0	0	0
T154	1135	0	0	0
T155	2678	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80347326	146	0	0
CgEnOn_A	80347326	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347326	146	0	0
T22	13064	0	0	0
T24	0	1	0	0
T31	996	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	493	0	0	0
T131	450	0	0	0
T132	815	0	0	0
T133	402	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	536	0	0	0
T153	584	0	0	0
T154	567	0	0	0
T155	1339	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347326	146	0	0
T22	13064	0	0	0
T24	0	1	0	0
T31	996	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	493	0	0	0
T131	450	0	0	0
T132	815	0	0	0
T133	402	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	536	0	0	0
T153	584	0	0	0
T154	567	0	0	0
T155	1339	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80347326	146	0	0
CgEnOn_A	80347326	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347326	146	0	0
T22	13064	0	0	0
T24	0	1	0	0
T31	996	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	493	0	0	0
T131	450	0	0	0
T132	815	0	0	0
T133	402	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	536	0	0	0
T153	584	0	0	0
T154	567	0	0	0
T155	1339	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347326	146	0	0
T22	13064	0	0	0
T24	0	1	0	0
T31	996	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	493	0	0	0
T131	450	0	0	0
T132	815	0	0	0
T133	402	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	536	0	0	0
T153	584	0	0	0
T154	567	0	0	0
T155	1339	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80347326	146	0	0
CgEnOn_A	80347326	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347326	146	0	0
T22	13064	0	0	0
T24	0	1	0	0
T31	996	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	493	0	0	0
T131	450	0	0	0
T132	815	0	0	0
T133	402	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	536	0	0	0
T153	584	0	0	0
T154	567	0	0	0
T155	1339	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347326	146	0	0
T22	13064	0	0	0
T24	0	1	0	0
T31	996	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	493	0	0	0
T131	450	0	0	0
T132	815	0	0	0
T133	402	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	536	0	0	0
T153	584	0	0	0
T154	567	0	0	0
T155	1339	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	323122392	146	0	0
CgEnOn_A	323122392	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323122392	146	0	0
T22	52376	0	0	0
T24	0	1	0	0
T31	4009	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	2009	0	0	0
T131	1832	0	0	0
T132	3217	0	0	0
T133	1647	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T152	2208	0	0	0
T153	2390	0	0	0
T154	2240	0	0	0
T155	5394	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323122392	143	0	0
T22	52376	0	0	0
T31	4009	1	0	0
T32	0	2	0	0
T33	0	3	0	0
T97	2009	0	0	0
T131	1832	0	0	0
T132	3217	0	0	0
T133	1647	0	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0
T152	2208	0	0	0
T153	2390	0	0	0
T154	2240	0	0	0
T155	5394	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	347199334	139	0	0
CgEnOn_A	347199334	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	139	0	0
T22	72559	0	0	0
T23	0	1	0	0
T31	4000	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T97	2092	0	0	0
T131	1908	0	0	0
T132	3351	0	0	0
T133	1716	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	3	0	0
T152	2301	0	0	0
T153	2489	0	0	0
T154	2334	0	0	0
T155	5619	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	138	0	0
T22	72559	0	0	0
T31	4000	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T97	2092	0	0	0
T131	1908	0	0	0
T132	3351	0	0	0
T133	1716	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	3	0	0
T151	0	3	0	0
T152	2301	0	0	0
T153	2489	0	0	0
T154	2334	0	0	0
T155	5619	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	347199334	139	0	0
CgEnOn_A	347199334	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	139	0	0
T22	72559	0	0	0
T23	0	1	0	0
T31	4000	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T97	2092	0	0	0
T131	1908	0	0	0
T132	3351	0	0	0
T133	1716	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	3	0	0
T152	2301	0	0	0
T153	2489	0	0	0
T154	2334	0	0	0
T155	5619	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	138	0	0
T22	72559	0	0	0
T31	4000	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T97	2092	0	0	0
T131	1908	0	0	0
T132	3351	0	0	0
T133	1716	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	3	0	0
T151	0	3	0	0
T152	2301	0	0	0
T153	2489	0	0	0
T154	2334	0	0	0
T155	5619	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	166639179	156	0	0
CgEnOn_A	166639179	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166639179	156	0	0
T22	37709	0	0	0
T31	2017	2	0	0
T32	0	1	0	0
T33	0	4	0	0
T97	1004	0	0	0
T131	915	0	0	0
T132	1609	0	0	0
T133	823	0	0	0
T145	0	1	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T152	1104	0	0	0
T153	1195	0	0	0
T154	1119	0	0	0
T155	2697	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166639179	154	0	0
T22	37709	0	0	0
T31	2017	2	0	0
T32	0	1	0	0
T33	0	4	0	0
T97	1004	0	0	0
T131	915	0	0	0
T132	1609	0	0	0
T133	823	0	0	0
T145	0	1	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	4	0	0
T152	1104	0	0	0
T153	1195	0	0	0
T154	1119	0	0	0
T155	2697	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80347326	8243	0	0
CgEnOn_A	80347326	5871	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347326	8243	0	0
T1	187715	7	0	0
T2	264073	113	0	0
T3	224208	71	0	0
T4	1080	2	0	0
T15	2822	6	0	0
T16	589	1	0	0
T17	2208	1	0	0
T18	428	1	0	0
T19	426	1	0	0
T20	1107	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347326	5871	0	0
T2	264073	102	0	0
T3	224208	66	0	0
T4	1080	1	0	0
T10	0	77	0	0
T11	0	29	0	0
T15	2822	0	0	0
T16	589	0	0	0
T17	2208	0	0	0
T18	428	0	0	0
T19	426	0	0	0
T20	1107	0	0	0
T21	0	3	0	0
T31	0	1	0	0
T41	0	14	0	0
T55	831	1	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	160695878	8322	0	0
CgEnOn_A	160695878	5950	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160695878	8322	0	0
T1	375431	7	0	0
T2	528148	112	0	0
T3	448418	71	0	0
T4	2160	2	0	0
T15	5644	6	0	0
T16	1179	1	0	0
T17	4420	1	0	0
T18	859	1	0	0
T19	854	1	0	0
T20	2213	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160695878	5950	0	0
T2	528148	101	0	0
T3	448418	66	0	0
T4	2160	1	0	0
T10	0	76	0	0
T11	0	32	0	0
T15	5644	0	0	0
T16	1179	0	0	0
T17	4420	0	0	0
T18	859	0	0	0
T19	854	0	0	0
T20	2213	0	0	0
T21	0	3	0	0
T31	0	1	0	0
T41	0	12	0	0
T55	1661	1	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	323122392	8352	0	0
CgEnOn_A	323122392	5977	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323122392	8352	0	0
T1	750308	7	0	0
T2	105642	119	0	0
T3	896856	72	0	0
T4	4440	2	0	0
T15	23419	6	0	0
T16	2464	1	0	0
T17	7923	1	0	0
T18	1706	1	0	0
T19	1728	1	0	0
T20	4492	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323122392	5977	0	0
T2	105642	108	0	0
T3	896856	67	0	0
T4	4440	1	0	0
T10	0	76	0	0
T11	0	28	0	0
T15	23419	0	0	0
T16	2464	0	0	0
T17	7923	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	4492	0	0	0
T21	0	3	0	0
T31	0	1	0	0
T41	0	11	0	0
T55	3416	1	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	166639179	8400	0	0
CgEnOn_A	166639179	6024	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166639179	8400	0	0
T1	401092	7	0	0
T2	544653	116	0	0
T3	460545	73	0	0
T4	2219	2	0	0
T15	11709	6	0	0
T16	1231	1	0	0
T17	3962	1	0	0
T18	853	1	0	0
T19	864	1	0	0
T20	2245	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166639179	6024	0	0
T2	544653	105	0	0
T3	460545	68	0	0
T4	2219	1	0	0
T10	0	77	0	0
T11	0	31	0	0
T15	11709	0	0	0
T16	1231	0	0	0
T17	3962	0	0	0
T18	853	0	0	0
T19	864	0	0	0
T20	2245	0	0	0
T21	0	3	0	0
T31	0	2	0	0
T41	0	13	0	0
T55	1707	1	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	347199334	4334	0	0
CgEnOn_A	347199334	4333	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	4334	0	0
T1	829595	11	0	0
T2	112927	96	0	0
T3	955855	74	0	0
T4	4624	1	0	0
T10	0	32	0	0
T11	0	33	0	0
T15	24396	0	0	0
T16	2566	6	0	0
T17	8253	0	0	0
T18	1778	0	0	0
T19	1800	0	0	0
T20	4679	0	0	0
T21	0	13	0	0
T56	0	10	0	0
T96	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	4333	0	0
T1	829595	11	0	0
T2	112927	96	0	0
T3	955855	74	0	0
T4	4624	1	0	0
T10	0	32	0	0
T11	0	33	0	0
T15	24396	0	0	0
T16	2566	6	0	0
T17	8253	0	0	0
T18	1778	0	0	0
T19	1800	0	0	0
T20	4679	0	0	0
T21	0	13	0	0
T56	0	10	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	347199334	4304	0	0
CgEnOn_A	347199334	4303	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	4304	0	0
T1	829595	13	0	0
T2	112927	92	0	0
T3	955855	75	0	0
T4	4624	1	0	0
T10	0	39	0	0
T11	0	29	0	0
T15	24396	0	0	0
T16	2566	5	0	0
T17	8253	0	0	0
T18	1778	0	0	0
T19	1800	0	0	0
T20	4679	0	0	0
T21	0	8	0	0
T56	0	11	0	0
T96	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	4303	0	0
T1	829595	13	0	0
T2	112927	92	0	0
T3	955855	75	0	0
T4	4624	1	0	0
T10	0	39	0	0
T11	0	29	0	0
T15	24396	0	0	0
T16	2566	5	0	0
T17	8253	0	0	0
T18	1778	0	0	0
T19	1800	0	0	0
T20	4679	0	0	0
T21	0	8	0	0
T56	0	11	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	347199334	4298	0	0
CgEnOn_A	347199334	4297	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	4298	0	0
T1	829595	14	0	0
T2	112927	93	0	0
T3	955855	79	0	0
T4	4624	1	0	0
T10	0	46	0	0
T11	0	33	0	0
T15	24396	0	0	0
T16	2566	6	0	0
T17	8253	0	0	0
T18	1778	0	0	0
T19	1800	0	0	0
T20	4679	0	0	0
T21	0	9	0	0
T56	0	10	0	0
T96	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	4297	0	0
T1	829595	14	0	0
T2	112927	93	0	0
T3	955855	79	0	0
T4	4624	1	0	0
T10	0	46	0	0
T11	0	33	0	0
T15	24396	0	0	0
T16	2566	6	0	0
T17	8253	0	0	0
T18	1778	0	0	0
T19	1800	0	0	0
T20	4679	0	0	0
T21	0	9	0	0
T56	0	10	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	347199334	4363	0	0
CgEnOn_A	347199334	4362	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	4363	0	0
T1	829595	17	0	0
T2	112927	97	0	0
T3	955855	83	0	0
T4	4624	1	0	0
T10	0	46	0	0
T11	0	31	0	0
T15	24396	0	0	0
T16	2566	4	0	0
T17	8253	0	0	0
T18	1778	0	0	0
T19	1800	0	0	0
T20	4679	0	0	0
T21	0	12	0	0
T56	0	12	0	0
T96	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199334	4362	0	0
T1	829595	17	0	0
T2	112927	97	0	0
T3	955855	83	0	0
T4	4624	1	0	0
T10	0	46	0	0
T11	0	31	0	0
T15	24396	0	0	0
T16	2566	4	0	0
T17	8253	0	0	0
T18	1778	0	0	0
T19	1800	0	0	0
T20	4679	0	0	0
T21	0	12	0	0
T56	0	12	0	0
T96	0	1	0	0