Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	622010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3540516

1

T5

30

T1

709

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1022847	1			T5	36		T1	304		T6	19
values[0x0]	1445360	1			T5	18		T1	669		T6	15
values[0x1]	1694319	1			T5	9		T1	674		T6	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	346264	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3816262

1

T5

33

T1

914

T6

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15912	1			T1	8		T4	2		T17	2
valid_sources[0x01]	17320	1			T1	4		T4	3		T19	2
valid_sources[0x02]	15784	1			T1	3		T2	6		T4	4
valid_sources[0x03]	17404	1			T5	1		T1	2		T4	3
valid_sources[0x04]	16001	1			T1	4		T4	4		T19	4
valid_sources[0x05]	16096	1			T1	3		T4	3		T20	1
valid_sources[0x06]	17072	1			T1	12		T4	4		T18	2
valid_sources[0x07]	15517	1			T1	5		T16	2		T4	2
valid_sources[0x08]	17501	1			T1	7		T4	1		T19	1
valid_sources[0x09]	15457	1			T1	8		T4	2		T19	3
valid_sources[0x0a]	16734	1			T1	7		T4	5		T3	9
valid_sources[0x0b]	15341	1			T1	4		T4	3		T19	1
valid_sources[0x0c]	17133	1			T1	6		T16	2		T4	4
valid_sources[0x0d]	17782	1			T1	5		T4	3		T19	1
valid_sources[0x0e]	16197	1			T5	1		T1	7		T4	2
valid_sources[0x0f]	17427	1			T1	6		T19	1		T41	2
valid_sources[0x10]	15989	1			T1	7		T4	3		T18	1
valid_sources[0x11]	15875	1			T1	10		T4	8		T3	1
valid_sources[0x12]	17787	1			T1	9		T6	14		T4	6
valid_sources[0x13]	16372	1			T1	6		T4	6		T3	1
valid_sources[0x14]	16242	1			T1	6		T4	4		T3	1
valid_sources[0x15]	15354	1			T5	1		T1	9		T4	1
valid_sources[0x16]	14520	1			T1	10		T4	1		T19	1
valid_sources[0x17]	15935	1			T1	5		T4	6		T3	4
valid_sources[0x18]	15051	1			T1	8		T16	1		T4	4
valid_sources[0x19]	16017	1			T1	1		T6	2		T4	1
valid_sources[0x1a]	15691	1			T1	1		T2	4		T4	2
valid_sources[0x1b]	19036	1			T1	4		T2	1		T4	2
valid_sources[0x1c]	15868	1			T1	4		T16	1		T4	5
valid_sources[0x1d]	16324	1			T1	1		T16	1		T4	3
valid_sources[0x1e]	15237	1			T1	4		T4	3		T3	4
valid_sources[0x1f]	15574	1			T1	1		T2	2		T4	4
valid_sources[0x20]	16288	1			T1	7		T4	1		T19	1
valid_sources[0x21]	16766	1			T5	1		T1	8		T4	4
valid_sources[0x22]	16927	1			T4	5		T18	1		T9	112
valid_sources[0x23]	16741	1			T1	11		T4	6		T3	5
valid_sources[0x24]	16035	1			T1	6		T4	3		T19	3
valid_sources[0x25]	16986	1			T1	4		T4	5		T19	3
valid_sources[0x26]	15238	1			T1	8		T4	3		T41	1
valid_sources[0x27]	17473	1			T1	12		T2	4		T4	1
valid_sources[0x28]	16796	1			T1	5		T4	2		T19	3
valid_sources[0x29]	16639	1			T5	1		T1	6		T4	2
valid_sources[0x2a]	16651	1			T1	5		T16	1		T4	2
valid_sources[0x2b]	16241	1			T1	7		T2	1		T4	1
valid_sources[0x2c]	17108	1			T1	6		T4	1		T19	1
valid_sources[0x2d]	15779	1			T5	4		T1	5		T16	3
valid_sources[0x2e]	18757	1			T1	5		T4	6		T3	4
valid_sources[0x2f]	15744	1			T1	5		T16	1		T4	2
valid_sources[0x30]	15134	1			T1	6		T4	4		T3	6
valid_sources[0x31]	15098	1			T1	6		T4	7		T17	1
valid_sources[0x32]	16355	1			T5	1		T1	12		T4	5
valid_sources[0x33]	17652	1			T1	6		T4	5		T19	1
valid_sources[0x34]	16261	1			T1	5		T4	5		T19	1
valid_sources[0x35]	16215	1			T1	4		T4	4		T19	1
valid_sources[0x36]	17035	1			T5	1		T1	3		T4	7
valid_sources[0x37]	15987	1			T5	1		T1	6		T4	2
valid_sources[0x38]	15883	1			T5	1		T1	9		T4	2
valid_sources[0x39]	16309	1			T1	2		T2	2		T4	3
valid_sources[0x3a]	17470	1			T1	6		T4	2		T3	9
valid_sources[0x3b]	15489	1			T1	11		T4	4		T19	3
valid_sources[0x3c]	15988	1			T1	7		T4	2		T3	1
valid_sources[0x3d]	16522	1			T1	7		T16	1		T4	4
valid_sources[0x3e]	16097	1			T5	2		T1	4		T19	1
valid_sources[0x3f]	17061	1			T1	12		T4	3		T3	12
valid_sources[0x40]	15785	1			T1	10		T4	4		T3	1
valid_sources[0x41]	16122	1			T5	2		T1	16		T16	2
valid_sources[0x42]	17940	1			T1	6		T4	3		T17	1
valid_sources[0x43]	16281	1			T1	2		T4	8		T19	1
valid_sources[0x44]	17269	1			T1	6		T4	3		T3	5
valid_sources[0x45]	16129	1			T1	4		T4	6		T9	118
valid_sources[0x46]	17099	1			T1	3		T4	5		T17	1
valid_sources[0x47]	15778	1			T1	11		T16	1		T4	6
valid_sources[0x48]	16430	1			T1	8		T4	3		T3	9
valid_sources[0x49]	15929	1			T1	1		T4	2		T41	2
valid_sources[0x4a]	15522	1			T1	5		T4	5		T9	85
valid_sources[0x4b]	14655	1			T1	4		T4	1		T17	1
valid_sources[0x4c]	15223	1			T1	4		T4	9		T19	1
valid_sources[0x4d]	16825	1			T1	5		T4	2		T18	1
valid_sources[0x4e]	17302	1			T5	2		T1	9		T6	7
valid_sources[0x4f]	16341	1			T1	3		T16	1		T4	1
valid_sources[0x50]	17283	1			T5	2		T1	10		T4	2
valid_sources[0x51]	17240	1			T1	7		T3	1		T17	2
valid_sources[0x52]	16982	1			T1	6		T4	5		T17	1
valid_sources[0x53]	15606	1			T1	6		T41	1		T9	109
valid_sources[0x54]	16439	1			T5	2		T1	4		T4	1
valid_sources[0x55]	16408	1			T5	1		T1	5		T4	3
valid_sources[0x56]	18046	1			T1	2		T4	7		T19	1
valid_sources[0x57]	16869	1			T1	1		T4	3		T41	1
valid_sources[0x58]	15721	1			T1	10		T4	1		T18	1
valid_sources[0x59]	15155	1			T1	7		T4	2		T9	137
valid_sources[0x5a]	15364	1			T5	1		T1	13		T4	2
valid_sources[0x5b]	17364	1			T5	1		T1	2		T4	3
valid_sources[0x5c]	15039	1			T1	6		T4	5		T3	2
valid_sources[0x5d]	17916	1			T1	3		T2	7		T4	7
valid_sources[0x5e]	16593	1			T1	3		T4	2		T3	1
valid_sources[0x5f]	16875	1			T1	11		T4	4		T3	8
valid_sources[0x60]	15445	1			T5	1		T1	2		T17	1
valid_sources[0x61]	15301	1			T1	3		T4	2		T19	2
valid_sources[0x62]	18976	1			T5	2		T1	6		T16	1
valid_sources[0x63]	15272	1			T1	7		T4	6		T3	2
valid_sources[0x64]	16768	1			T1	9		T4	1		T3	4
valid_sources[0x65]	16113	1			T1	2		T4	3		T3	1
valid_sources[0x66]	15696	1			T1	12		T4	1		T20	1
valid_sources[0x67]	18602	1			T1	6		T16	1		T4	2
valid_sources[0x68]	15536	1			T1	12		T4	2		T19	2
valid_sources[0x69]	15391	1			T1	6		T4	3		T3	4
valid_sources[0x6a]	15918	1			T1	4		T4	4		T19	1
valid_sources[0x6b]	15144	1			T1	10		T4	3		T9	126
valid_sources[0x6c]	16259	1			T1	2		T4	4		T3	1
valid_sources[0x6d]	17240	1			T1	7		T4	7		T3	3
valid_sources[0x6e]	16568	1			T1	7		T4	3		T3	2
valid_sources[0x6f]	17782	1			T1	4		T4	4		T9	125
valid_sources[0x70]	16019	1			T5	4		T1	13		T2	1
valid_sources[0x71]	16815	1			T1	11		T16	2		T4	2
valid_sources[0x72]	16826	1			T1	10		T16	1		T4	3
valid_sources[0x73]	18523	1			T1	14		T16	2		T4	2
valid_sources[0x74]	14855	1			T5	3		T1	4		T4	4
valid_sources[0x75]	16623	1			T1	5		T4	2		T19	3
valid_sources[0x76]	16583	1			T1	6		T4	1		T3	1
valid_sources[0x77]	15563	1			T1	6		T4	1		T3	3
valid_sources[0x78]	16432	1			T1	10		T4	3		T3	4
valid_sources[0x79]	17813	1			T1	3		T4	2		T9	139
valid_sources[0x7a]	16801	1			T1	9		T4	6		T41	1
valid_sources[0x7b]	16282	1			T1	10		T3	1		T17	1
valid_sources[0x7c]	16154	1			T1	1		T4	4		T3	5
valid_sources[0x7d]	15686	1			T1	6		T4	3		T3	3
valid_sources[0x7e]	15355	1			T1	7		T4	3		T3	2
valid_sources[0x7f]	15461	1			T1	7		T4	2		T9	109
valid_sources[0x80]	17020	1			T5	1		T1	6		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

893683

1

T5

21

T1

148

T6

13

values[0x0]

all_enables

biggest_size

1347964

1

T5

6

T1

348

T6

4

values[0x1]

all_enables

biggest_size

1298869

1

T5

3

T1

213

T6

1