Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T41
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T41
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	911858441	14892	0	0
GateOpen_A	911858441	21434	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	911858441	14892	0	0
T1	1469059	195	0	0
T2	74764	0	0	0
T3	384751	0	0	0
T4	543350	87	0	0
T6	4836	0	0	0
T9	0	193	0	0
T16	7986	0	0	0
T17	34162	0	0	0
T18	11056	0	0	0
T19	265354	0	0	0
T20	8098	0	0	0
T21	0	4	0	0
T36	0	9	0	0
T37	0	11	0	0
T41	0	2	0	0
T45	0	6	0	0
T47	0	18	0	0
T154	0	7	0	0
T155	0	19	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	911858441	21434	0	0
T1	1469059	215	0	0
T2	74764	0	0	0
T3	384751	4	0	0
T4	543350	119	0	0
T5	48430	4	0	0
T6	4836	0	0	0
T9	0	211	0	0
T16	7986	4	0	0
T17	34162	0	0	0
T18	11056	0	0	0
T19	265354	0	0	0
T36	0	13	0	0
T40	0	204	0	0
T41	0	6	0	0
T102	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T9
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	100434903	3510	0	0
GateOpen_A	100434903	5143	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434903	3510	0	0
T1	162162	49	0	0
T2	8303	0	0	0
T3	42744	0	0	0
T4	60410	24	0	0
T6	555	0	0	0
T9	0	46	0	0
T16	870	0	0	0
T17	4133	0	0	0
T18	1337	0	0	0
T19	29468	0	0	0
T20	953	0	0	0
T21	0	1	0	0
T36	0	2	0	0
T37	0	3	0	0
T45	0	2	0	0
T47	0	5	0	0
T154	0	2	0	0
T155	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434903	5143	0	0
T1	162162	54	0	0
T2	8303	0	0	0
T3	42744	1	0	0
T4	60410	32	0	0
T5	5373	1	0	0
T6	555	0	0	0
T9	0	50	0	0
T16	870	1	0	0
T17	4133	0	0	0
T18	1337	0	0	0
T19	29468	0	0	0
T36	0	3	0	0
T40	0	51	0	0
T41	0	1	0	0
T102	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T41
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T41
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	200870614	3799	0	0
GateOpen_A	200870614	5432	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200870614	3799	0	0
T1	324322	48	0	0
T2	16606	0	0	0
T3	85487	0	0	0
T4	120822	23	0	0
T6	1111	0	0	0
T9	0	47	0	0
T16	1739	0	0	0
T17	8265	0	0	0
T18	2676	0	0	0
T19	58936	0	0	0
T20	1905	0	0	0
T21	0	1	0	0
T36	0	2	0	0
T37	0	3	0	0
T41	0	1	0	0
T45	0	1	0	0
T47	0	4	0	0
T154	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200870614	5432	0	0
T1	324322	53	0	0
T2	16606	0	0	0
T3	85487	1	0	0
T4	120822	31	0	0
T5	10745	1	0	0
T6	1111	0	0	0
T9	0	51	0	0
T16	1739	1	0	0
T17	8265	0	0	0
T18	2676	0	0	0
T19	58936	0	0	0
T36	0	3	0	0
T40	0	51	0	0
T41	0	2	0	0
T102	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T41
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T41
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	403443673	3778	0	0
GateOpen_A	403443673	5416	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403443673	3778	0	0
T1	649279	45	0	0
T2	33236	0	0	0
T3	171011	0	0	0
T4	241408	19	0	0
T6	2113	0	0	0
T9	0	53	0	0
T16	3585	0	0	0
T17	14509	0	0	0
T18	4695	0	0	0
T19	117965	0	0	0
T20	3493	0	0	0
T21	0	1	0	0
T36	0	2	0	0
T37	0	3	0	0
T41	0	1	0	0
T45	0	1	0	0
T47	0	4	0	0
T154	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403443673	5416	0	0
T1	649279	50	0	0
T2	33236	0	0	0
T3	171011	1	0	0
T4	241408	27	0	0
T5	21541	1	0	0
T6	2113	0	0	0
T9	0	58	0	0
T16	3585	1	0	0
T17	14509	0	0	0
T18	4695	0	0	0
T19	117965	0	0	0
T36	0	3	0	0
T40	0	51	0	0
T41	0	2	0	0
T102	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T9
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	207109251	3805	0	0
GateOpen_A	207109251	5443	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207109251	3805	0	0
T1	333296	53	0	0
T2	16619	0	0	0
T3	85509	0	0	0
T4	120710	21	0	0
T6	1057	0	0	0
T9	0	47	0	0
T16	1792	0	0	0
T17	7255	0	0	0
T18	2348	0	0	0
T19	58985	0	0	0
T20	1747	0	0	0
T21	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T45	0	2	0	0
T47	0	5	0	0
T154	0	2	0	0
T155	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207109251	5443	0	0
T1	333296	58	0	0
T2	16619	0	0	0
T3	85509	1	0	0
T4	120710	29	0	0
T5	10771	1	0	0
T6	1057	0	0	0
T9	0	52	0	0
T16	1792	1	0	0
T17	7255	0	0	0
T18	2348	0	0	0
T19	58985	0	0	0
T36	0	4	0	0
T40	0	51	0	0
T41	0	1	0	0
T102	0	1	0	0