Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	833513385	89648	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	833513385	89648	0	0
T1	543260	88	0	0
T2	41540	50	0	0
T3	115795	41	0	0
T4	141610	0	0	0
T6	10675	0	0	0
T9	0	1283	0	0
T10	0	57	0	0
T11	0	582	0	0
T12	0	1347	0	0
T13	0	63	0	0
T14	0	443	0	0
T15	0	51	0	0
T16	12130	0	0	0
T17	7550	0	0	0
T18	11740	0	0	0
T19	129030	0	0	0
T20	8915	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166702677	13063	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	13063	0	0
T1	108652	15	0	0
T2	8308	8	0	0
T3	23159	7	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	188	0	0
T10	0	9	0	0
T11	0	94	0	0
T12	0	170	0	0
T13	0	9	0	0
T14	0	64	0	0
T15	0	8	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	0	0	0
T20	1783	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166702677	12584	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	12584	0	0
T1	108652	15	0	0
T2	8308	8	0	0
T3	23159	7	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	161	0	0
T10	0	8	0	0
T11	0	93	0	0
T12	0	194	0	0
T13	0	9	0	0
T14	0	63	0	0
T15	0	8	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	0	0	0
T20	1783	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166702677	18072	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	18072	0	0
T1	108652	19	0	0
T2	8308	10	0	0
T3	23159	8	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	254	0	0
T10	0	12	0	0
T11	0	118	0	0
T12	0	265	0	0
T13	0	13	0	0
T14	0	88	0	0
T15	0	10	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	0	0	0
T20	1783	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166702677	18022	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	18022	0	0
T1	108652	17	0	0
T2	8308	10	0	0
T3	23159	8	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	255	0	0
T10	0	11	0	0
T11	0	118	0	0
T12	0	271	0	0
T13	0	13	0	0
T14	0	89	0	0
T15	0	10	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	0	0	0
T20	1783	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	166702677	27907	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	27907	0	0
T1	108652	22	0	0
T2	8308	14	0	0
T3	23159	11	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	425	0	0
T10	0	17	0	0
T11	0	159	0	0
T12	0	447	0	0
T13	0	19	0	0
T14	0	139	0	0
T15	0	15	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	0	0	0
T20	1783	0	0	0