Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T4,T9

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	166702677	163894230	0	0
AllClkBypReqTrue_A	166702677	129767	0	0
IoClkBypReqFalse_A	166702677	163816403	0	2415
IoClkBypReqTrue_A	166702677	202934	0	0
LcClkBypAckFalse_A	166702677	163905639	0	0
LcClkBypAckTrue_A	166702677	118358	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	163894230	0	0
T1	108652	108472	0	0
T2	8308	8281	0	0
T3	23159	23138	0	0
T4	28322	28026	0	0
T5	1571	1556	0	0
T6	2135	1629	0	0
T16	2426	2288	0	0
T17	1510	1363	0	0
T18	2348	1838	0	0
T19	25806	25773	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	129767	0	0
T2	8308	0	0	0
T3	23159	0	0	0
T4	28322	118	0	0
T6	2135	286	0	0
T9	0	1260	0	0
T16	2426	0	0	0
T17	1510	120	0	0
T18	2348	407	0	0
T19	25806	0	0	0
T20	1783	180	0	0
T46	0	80	0	0
T48	0	61	0	0
T49	0	130	0	0
T50	0	36	0	0
T102	1316	0	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	163816403	0	2415
T1	108652	108456	0	3
T2	8308	8279	0	3
T3	23159	23136	0	3
T4	28322	28016	0	3
T5	1571	1554	0	3
T6	2135	1581	0	3
T16	2426	2286	0	3
T17	1510	1267	0	3
T18	2348	1708	0	3
T19	25806	25771	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	202934	0	0
T2	8308	0	0	0
T3	23159	0	0	0
T4	28322	112	0	0
T6	2135	332	0	0
T9	0	1696	0	0
T16	2426	0	0	0
T17	1510	214	0	0
T18	2348	535	0	0
T19	25806	0	0	0
T20	1783	82	0	0
T46	0	94	0	0
T48	0	44	0	0
T49	0	204	0	0
T102	1316	142	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	163905639	0	0
T1	108652	108472	0	0
T2	8308	8281	0	0
T3	23159	23138	0	0
T4	28322	28042	0	0
T5	1571	1556	0	0
T6	2135	1759	0	0
T16	2426	2288	0	0
T17	1510	1305	0	0
T18	2348	1935	0	0
T19	25806	25773	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	118358	0	0
T2	8308	0	0	0
T3	23159	0	0	0
T4	28322	102	0	0
T6	2135	156	0	0
T9	0	1027	0	0
T16	2426	0	0	0
T17	1510	178	0	0
T18	2348	310	0	0
T19	25806	0	0	0
T20	1783	76	0	0
T46	0	13	0	0
T48	0	39	0	0
T49	0	110	0	0
T102	1316	75	0	0