Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1725722460	16593	0	0
TransStop_A	1725722460	8561	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1725722460	16593	0	0
T1	2777416	102	0	0
T2	138488	0	0	0
T3	712572	0	0	0
T4	981904	152	0	0
T5	89760	17	0	0
T6	8808	0	0	0
T9	0	195	0	0
T16	14936	19	0	0
T17	60460	0	0	0
T18	19568	0	0	0
T19	491536	0	0	0
T21	0	59	0	0
T41	0	4	0	0
T51	0	5	0	0
T69	0	39	0	0
T103	0	29	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1725722460	8561	0	0
T1	2777416	66	0	0
T2	138488	0	0	0
T3	712572	0	0	0
T4	981904	97	0	0
T5	89760	10	0	0
T6	8808	0	0	0
T9	0	94	0	0
T16	14936	12	0	0
T17	60460	0	0	0
T18	19568	0	0	0
T19	491536	0	0	0
T21	0	15	0	0
T41	0	4	0	0
T51	0	2	0	0
T69	0	23	0	0
T103	0	13	0	0
T104	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	431430615	4170	0	0
TransStop_A	431430615	2183	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430615	4170	0	0
T1	694354	24	0	0
T2	34622	0	0	0
T3	178143	0	0	0
T4	245476	37	0	0
T5	22440	5	0	0
T6	2202	0	0	0
T9	0	44	0	0
T16	3734	2	0	0
T17	15115	0	0	0
T18	4892	0	0	0
T19	122884	0	0	0
T21	0	11	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	11	0	0
T103	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430615	2183	0	0
T1	694354	16	0	0
T2	34622	0	0	0
T3	178143	0	0	0
T4	245476	25	0	0
T5	22440	3	0	0
T6	2202	0	0	0
T9	0	24	0	0
T16	3734	2	0	0
T17	15115	0	0	0
T18	4892	0	0	0
T19	122884	0	0	0
T21	0	4	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	9	0	0
T103	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	431430615	4147	0	0
TransStop_A	431430615	2135	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430615	4147	0	0
T1	694354	25	0	0
T2	34622	0	0	0
T3	178143	0	0	0
T4	245476	33	0	0
T5	22440	2	0	0
T6	2202	0	0	0
T9	0	53	0	0
T16	3734	6	0	0
T17	15115	0	0	0
T18	4892	0	0	0
T19	122884	0	0	0
T21	0	16	0	0
T41	0	1	0	0
T51	0	2	0	0
T69	0	12	0	0
T103	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430615	2135	0	0
T1	694354	17	0	0
T2	34622	0	0	0
T3	178143	0	0	0
T4	245476	23	0	0
T5	22440	1	0	0
T6	2202	0	0	0
T9	0	22	0	0
T16	3734	3	0	0
T17	15115	0	0	0
T18	4892	0	0	0
T19	122884	0	0	0
T21	0	3	0	0
T41	0	1	0	0
T69	0	5	0	0
T103	0	3	0	0
T104	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	431430615	4157	0	0
TransStop_A	431430615	2121	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430615	4157	0	0
T1	694354	25	0	0
T2	34622	0	0	0
T3	178143	0	0	0
T4	245476	40	0	0
T5	22440	4	0	0
T6	2202	0	0	0
T9	0	49	0	0
T16	3734	7	0	0
T17	15115	0	0	0
T18	4892	0	0	0
T19	122884	0	0	0
T21	0	17	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	5	0	0
T103	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430615	2121	0	0
T1	694354	16	0	0
T2	34622	0	0	0
T3	178143	0	0	0
T4	245476	24	0	0
T5	22440	2	0	0
T6	2202	0	0	0
T9	0	23	0	0
T16	3734	4	0	0
T17	15115	0	0	0
T18	4892	0	0	0
T19	122884	0	0	0
T21	0	5	0	0
T41	0	1	0	0
T69	0	3	0	0
T103	0	3	0	0
T104	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	431430615	4119	0	0
TransStop_A	431430615	2122	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430615	4119	0	0
T1	694354	28	0	0
T2	34622	0	0	0
T3	178143	0	0	0
T4	245476	42	0	0
T5	22440	6	0	0
T6	2202	0	0	0
T9	0	49	0	0
T16	3734	4	0	0
T17	15115	0	0	0
T18	4892	0	0	0
T19	122884	0	0	0
T21	0	15	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	11	0	0
T103	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430615	2122	0	0
T1	694354	17	0	0
T2	34622	0	0	0
T3	178143	0	0	0
T4	245476	25	0	0
T5	22440	4	0	0
T6	2202	0	0	0
T9	0	25	0	0
T16	3734	3	0	0
T17	15115	0	0	0
T18	4892	0	0	0
T19	122884	0	0	0
T21	0	3	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	6	0	0
T103	0	4	0	0