Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T1,T6
01CoveredT5,T1,T6
10CoveredT6,T4,T17 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T1,T6
10CoveredT6,T4,T17
11CoveredT6,T4,T17 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T4,T17
10CoveredT5,T1,T6
11CoveredT5,T1,T6
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 501920179 501917764 0 0
selKnown1 1210329756 1210327341 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 501920179 501917764 0 0
T1 810803 810800 0 0
T2 41513 41510 0 0
T3 213715 213712 0 0
T4 301526 301523 0 0
T5 26862 26859 0 0
T6 2653 2650 0 0
T16 4345 4342 0 0
T17 19590 19587 0 0
T18 6314 6311 0 0
T19 147340 147337 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1210329756 1210327341 0 0
T1 1947834 1947831 0 0
T2 99705 99702 0 0
T3 513030 513027 0 0
T4 724224 724221 0 0
T5 64623 64620 0 0
T6 6339 6336 0 0
T16 10752 10749 0 0
T17 43527 43524 0 0
T18 14082 14079 0 0
T19 353895 353892 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T1,T6
01CoveredT5,T1,T6
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T1,T6
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT5,T1,T6
11CoveredT5,T1,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 200870208 200869403 0 0
selKnown1 403443252 403442447 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 200870208 200869403 0 0
T1 324321 324320 0 0
T2 16605 16604 0 0
T3 85486 85485 0 0
T4 120821 120820 0 0
T5 10745 10744 0 0
T6 1110 1109 0 0
T16 1738 1737 0 0
T17 8264 8263 0 0
T18 2676 2675 0 0
T19 58936 58935 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 403443252 403442447 0 0
T1 649278 649277 0 0
T2 33235 33234 0 0
T3 171010 171009 0 0
T4 241408 241407 0 0
T5 21541 21540 0 0
T6 2113 2112 0 0
T16 3584 3583 0 0
T17 14509 14508 0 0
T18 4694 4693 0 0
T19 117965 117964 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T1,T6
01CoveredT5,T1,T6
10CoveredT6,T4,T17 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T1,T6
10CoveredT6,T4,T17
11CoveredT6,T4,T17 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T4,T17
10CoveredT5,T1,T6
11CoveredT5,T1,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 200615460 200614655 0 0
selKnown1 403443252 403442447 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 200615460 200614655 0 0
T1 324321 324320 0 0
T2 16605 16604 0 0
T3 85486 85485 0 0
T4 120295 120294 0 0
T5 10745 10744 0 0
T6 989 988 0 0
T16 1738 1737 0 0
T17 7194 7193 0 0
T18 2301 2300 0 0
T19 58936 58935 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 403443252 403442447 0 0
T1 649278 649277 0 0
T2 33235 33234 0 0
T3 171010 171009 0 0
T4 241408 241407 0 0
T5 21541 21540 0 0
T6 2113 2112 0 0
T16 3584 3583 0 0
T17 14509 14508 0 0
T18 4694 4693 0 0
T19 117965 117964 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T1,T6
01CoveredT5,T1,T6
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T1,T6
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT5,T1,T6
11CoveredT5,T1,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 100434511 100433706 0 0
selKnown1 403443252 403442447 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 100434511 100433706 0 0
T1 162161 162160 0 0
T2 8303 8302 0 0
T3 42743 42742 0 0
T4 60410 60409 0 0
T5 5372 5371 0 0
T6 554 553 0 0
T16 869 868 0 0
T17 4132 4131 0 0
T18 1337 1336 0 0
T19 29468 29467 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 403443252 403442447 0 0
T1 649278 649277 0 0
T2 33235 33234 0 0
T3 171010 171009 0 0
T4 241408 241407 0 0
T5 21541 21540 0 0
T6 2113 2112 0 0
T16 3584 3583 0 0
T17 14509 14508 0 0
T18 4694 4693 0 0
T19 117965 117964 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%