Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	166702677	18663949	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	18663949	0	57
T1	108652	5363	0	0
T2	8308	3753	0	1
T3	23159	2470	0	1
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	145044	0	0
T10	0	6095	0	1
T11	0	905151	0	0
T12	0	158047	0	0
T13	0	0	0	1
T15	0	0	0	1
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	778	0	1
T20	1783	0	0	0
T21	0	744	0	0
T23	0	827	0	0
T24	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1
T107	0	0	0	1