Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	167583358	5138995	0	0
clk_enables_rd_A	167583358	56855	0	0
clk_hints_rd_A	167583358	50050	0	0
extclk_ctrl_rd_A	167583358	63106	0	0
extclk_ctrl_regwen_rd_A	167583358	47886	0	0
jitter_enable_rd_A	167583358	71516	0	0
jitter_regwen_rd_A	167583358	54050	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	5138995	0	0
T9	131608	36926	0	0
T10	18932	0	0	0
T11	0	93080	0	0
T26	0	93627	0	0
T27	0	145963	0	0
T29	1680	0	0	0
T36	1409	0	0	0
T37	1187	0	0	0
T39	0	57510	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T64	0	69043	0	0
T65	0	118988	0	0
T66	0	109834	0	0
T67	0	110922	0	0
T68	0	43308	0	0
T69	2463	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	56855	0	0
T9	131608	1557	0	0
T10	18932	0	0	0
T27	0	5746	0	0
T29	1680	0	0	0
T36	1409	0	0	0
T37	1187	0	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T64	0	2803	0	0
T65	0	5029	0	0
T69	2463	0	0	0
T107	0	1	0	0
T131	0	5	0	0
T132	0	4	0	0
T133	0	5	0	0
T134	0	7	0	0
T135	0	2348	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	50050	0	0
T9	131608	1296	0	0
T10	18932	0	0	0
T27	0	4816	0	0
T29	1680	0	0	0
T36	1409	0	0	0
T37	1187	0	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T64	0	2351	0	0
T65	0	4146	0	0
T69	2463	0	0	0
T107	0	10	0	0
T131	0	4	0	0
T132	0	6	0	0
T133	0	5	0	0
T134	0	7	0	0
T135	0	2184	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	63106	0	0
T2	8308	0	0	0
T3	23159	0	0	0
T4	28322	0	0	0
T6	2135	18	0	0
T9	0	1797	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	58	0	0
T19	25806	0	0	0
T20	1783	41	0	0
T48	0	8	0	0
T50	0	32	0	0
T52	0	28	0	0
T102	1316	0	0	0
T136	0	21	0	0
T137	0	59	0	0
T138	0	10	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	47886	0	0
T9	131608	1214	0	0
T10	18932	0	0	0
T27	0	4780	0	0
T29	1680	0	0	0
T36	1409	0	0	0
T37	1187	0	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T64	0	2441	0	0
T65	0	4041	0	0
T69	2463	0	0	0
T93	0	10	0	0
T135	0	2112	0	0
T139	0	62	0	0
T140	0	11	0	0
T141	0	16	0	0
T142	0	2538	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	71516	0	0
T1	108652	63	0	0
T2	8308	0	0	0
T3	23159	0	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	1961	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	0	0	0
T20	1783	0	0	0
T27	0	5712	0	0
T64	0	3624	0	0
T65	0	5861	0	0
T107	0	234	0	0
T131	0	81	0	0
T132	0	119	0	0
T133	0	105	0	0
T134	0	86	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	54050	0	0
T9	131608	1279	0	0
T10	18932	0	0	0
T27	0	5372	0	0
T29	1680	0	0	0
T36	1409	0	0	0
T37	1187	0	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T64	0	2794	0	0
T65	0	4551	0	0
T69	2463	0	0	0
T135	0	2481	0	0
T142	0	3032	0	0
T143	0	3840	0	0
T144	0	2916	0	0
T145	0	2119	0	0
T146	0	2163	0	0