Unified Coverage Report :: Module :: prim_sync_reqack

Module : prim_sync_reqack

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	50.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_io_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_io_div2_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_io_div4_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_main_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_usb_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00

---

Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.61	90.00	76.19			78.26	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.61	90.00	76.19			78.26	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.17	94.00	85.71			86.96	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.61	90.00	76.19			78.26	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.61	90.00	76.19			78.26	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

Line Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_sync_reqack

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T1,T6

---

Branch Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Module : prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	2147483647	16277198	0	0
SyncReqAckHoldReq	2147483647	146242	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16277198	0	0
T1	3249928	8483	0	0
T2	192462	75	0	0
T3	794480	400	0	0
T4	1072043	10765	0	0
T5	70868	1385	0	0
T6	28384	123	0	0
T9	0	244	0	0
T10	0	16	0	0
T11	0	50	0	0
T12	0	58	0	0
T13	0	7	0	0
T14	0	81	0	0
T15	0	4	0	0
T16	35975	214	0	0
T17	64373	935	0	0
T18	39426	284	0	0
T19	646297	279	0	0
T20	17830	0	0	0
T21	0	51	0	0
T22	0	40	0	0
T23	0	10	0	0
T24	0	38	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	146242	0	0
T1	4326816	527	0	0
T2	218764	34	0	0
T3	1125780	186	0	0
T4	1577646	60	0	0
T6	14068	0	0	0
T9	0	864	0	0
T10	0	47	0	0
T11	0	57	0	0
T12	0	62	0	0
T13	0	10	0	0
T14	0	113	0	0
T15	0	8	0	0
T16	23430	0	0	0
T17	98546	0	0	0
T18	31892	0	0	0
T19	776474	127	0	0
T20	23466	0	0	0
T21	0	243	0	0
T22	0	200	0	0
T23	0	10	0	0
T24	0	44	0	0
T25	0	70	0	0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T1,T6

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	403443252	3253890	0	0
SyncReqAckHoldReq	14694368	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	403443252	3253890	0	0
T1	649278	2103	0	0
T2	33235	17	0	0
T3	171010	82	0	0
T4	241408	2721	0	0
T5	21541	350	0	0
T6	2113	31	0	0
T16	3584	54	0	0
T17	14509	236	0	0
T18	4694	72	0	0
T19	117965	58	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	14694368	0	0	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T1,T6

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	200870208	3253785	0	0
SyncReqAckHoldReq	14694368	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	200870208	3253785	0	0
T1	324321	2102	0	0
T2	16605	17	0	0
T3	85486	82	0	0
T4	120821	2721	0	0
T5	10745	350	0	0
T6	1110	31	0	0
T16	1738	54	0	0
T17	8264	236	0	0
T18	2676	72	0	0
T19	58936	58	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	14694368	0	0	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T1,T6

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	100434511	3100408	0	0
SyncReqAckHoldReq	14694368	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	3100408	0	0
T1	162161	2022	0	0
T2	8303	17	0	0
T3	42743	82	0	0
T4	60410	2591	0	0
T5	5372	335	0	0
T6	554	30	0	0
T16	869	52	0	0
T17	4132	227	0	0
T18	1337	68	0	0
T19	29468	58	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	14694368	0	0	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T1,T6

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	431430169	3258206	0	0
SyncReqAckHoldReq	14694368	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	3258206	0	0
T1	694353	2110	0	0
T2	34621	17	0	0
T3	178142	82	0	0
T4	245475	2720	0	0
T5	22439	350	0	0
T6	2201	31	0	0
T16	3733	54	0	0
T17	15114	236	0	0
T18	4891	72	0	0
T19	122883	58	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	14694368	0	0	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T1,T6

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T1,T6
EVEN	0	-	Covered	T5,T1,T6
ODD	-	1	Covered	T5,T1,T6
ODD	-	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	207108858	3258134	0	0
SyncReqAckHoldReq	14694368	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108858	3258134	0	0
T1	333295	2108	0	0
T2	16618	17	0	0
T3	85509	82	0	0
T4	120709	2721	0	0
T5	10771	350	0	0
T6	1056	31	0	0
T16	1791	54	0	0
T17	7254	236	0	0
T18	2348	72	0	0
T19	58985	58	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	14694368	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	167583358	27524	0	0
SyncReqAckHoldReq	405912705	26250	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	27524	0	0
T1	108652	94	0	0
T2	8308	7	0	0
T3	23159	29	0	0
T4	28322	12	0	0
T6	2135	0	0	0
T9	0	163	0	0
T10	0	9	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	20	0	0
T20	1783	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	405912705	26250	0	0
T1	649278	92	0	0
T2	33235	6	0	0
T3	171010	28	0	0
T4	241408	12	0	0
T6	2113	0	0	0
T9	0	151	0	0
T10	0	8	0	0
T16	3584	0	0	0
T17	14509	0	0	0
T18	4694	0	0	0
T19	117965	20	0	0
T20	3493	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	167583358	27524	0	0
SyncReqAckHoldReq	202061038	26246	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	27524	0	0
T1	108652	94	0	0
T2	8308	7	0	0
T3	23159	29	0	0
T4	28322	12	0	0
T6	2135	0	0	0
T9	0	163	0	0
T10	0	9	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	20	0	0
T20	1783	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	202061038	26246	0	0
T1	324321	92	0	0
T2	16605	6	0	0
T3	85486	28	0	0
T4	120821	12	0	0
T6	1110	0	0	0
T9	0	151	0	0
T10	0	8	0	0
T16	1738	0	0	0
T17	8264	0	0	0
T18	2676	0	0	0
T19	58936	20	0	0
T20	1904	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	167583358	27524	0	0
SyncReqAckHoldReq	101029914	26212	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	27524	0	0
T1	108652	94	0	0
T2	8308	7	0	0
T3	23159	29	0	0
T4	28322	12	0	0
T6	2135	0	0	0
T9	0	163	0	0
T10	0	9	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	20	0	0
T20	1783	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	101029914	26212	0	0
T1	162161	92	0	0
T2	8303	6	0	0
T3	42743	28	0	0
T4	60410	12	0	0
T6	554	0	0	0
T9	0	151	0	0
T10	0	8	0	0
T16	869	0	0	0
T17	4132	0	0	0
T18	1337	0	0	0
T19	29468	20	0	0
T20	952	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	167583358	27524	0	0
SyncReqAckHoldReq	434002628	26250	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	27524	0	0
T1	108652	94	0	0
T2	8308	7	0	0
T3	23159	29	0	0
T4	28322	12	0	0
T6	2135	0	0	0
T9	0	163	0	0
T10	0	9	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	20	0	0
T20	1783	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	434002628	26250	0	0
T1	694353	92	0	0
T2	34621	6	0	0
T3	178142	28	0	0
T4	245475	12	0	0
T6	2201	0	0	0
T9	0	151	0	0
T10	0	8	0	0
T16	3733	0	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	20	0	0
T20	3638	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	167583358	27058	0	0
SyncReqAckHoldReq	208343616	25663	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	167583358	27058	0	0
T1	108652	94	0	0
T2	8308	7	0	0
T3	23159	29	0	0
T4	28322	12	0	0
T6	2135	0	0	0
T9	0	163	0	0
T10	0	9	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	20	0	0
T20	1783	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	208343616	25663	0	0
T1	333295	92	0	0
T2	16618	6	0	0
T3	85509	28	0	0
T4	120709	12	0	0
T6	1056	0	0	0
T9	0	151	0	0
T10	0	8	0	0
T16	1791	0	0	0
T17	7254	0	0	0
T18	2348	0	0	0
T19	58985	20	0	0
T20	1746	0	0	0
T21	0	48	0	0
T22	0	40	0	0
T25	0	14	0	0

Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T3,T19

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T19

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T3,T19
EVEN	0	-	Covered	T1,T3,T19
ODD	-	1	Covered	T1,T3,T19
ODD	-	0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T3,T19
EVEN	0	-	Covered	T1,T3,T19
ODD	-	1	Covered	T1,T3,T19
ODD	-	0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	166702677	3252	0	0
SyncReqAckHoldReq	403443252	3252	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	3252	0	0
T1	108652	14	0	0
T2	8308	0	0	0
T3	23159	22	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	17	0	0
T11	0	14	0	0
T12	0	26	0	0
T13	0	3	0	0
T14	0	11	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	5	0	0
T20	1783	0	0	0
T23	0	7	0	0
T24	0	24	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	403443252	3252	0	0
T1	649278	14	0	0
T2	33235	0	0	0
T3	171010	22	0	0
T4	241408	0	0	0
T6	2113	0	0	0
T9	0	17	0	0
T11	0	14	0	0
T12	0	26	0	0
T13	0	3	0	0
T14	0	11	0	0
T16	3584	0	0	0
T17	14509	0	0	0
T18	4694	0	0	0
T19	117965	5	0	0
T20	3493	0	0	0
T23	0	7	0	0
T24	0	24	0	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T3,T19

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T19

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T3,T19
EVEN	0	-	Covered	T1,T3,T19
ODD	-	1	Covered	T1,T3,T19
ODD	-	0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T3,T19
EVEN	0	-	Covered	T1,T3,T19
ODD	-	1	Covered	T1,T3,T19
ODD	-	0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	166702677	3261	0	0
SyncReqAckHoldReq	200870208	3261	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	3261	0	0
T1	108652	23	0	0
T2	8308	0	0	0
T3	23159	9	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	29	0	0
T10	0	4	0	0
T11	0	15	0	0
T12	0	8	0	0
T13	0	4	0	0
T14	0	14	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	8	0	0
T20	1783	0	0	0
T24	0	3	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	200870208	3261	0	0
T1	324321	23	0	0
T2	16605	0	0	0
T3	85486	9	0	0
T4	120821	0	0	0
T6	1110	0	0	0
T9	0	29	0	0
T10	0	4	0	0
T11	0	15	0	0
T12	0	8	0	0
T13	0	4	0	0
T14	0	14	0	0
T16	1738	0	0	0
T17	8264	0	0	0
T18	2676	0	0	0
T19	58936	8	0	0
T20	1904	0	0	0
T24	0	3	0	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T3,T19

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T19

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T3,T19
EVEN	0	-	Covered	T1,T3,T19
ODD	-	1	Covered	T1,T3,T19
ODD	-	0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T3,T19
EVEN	0	-	Covered	T1,T3,T19
ODD	-	1	Covered	T1,T3,T19
ODD	-	0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	166702677	3104	0	0
SyncReqAckHoldReq	100434511	3104	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	3104	0	0
T1	108652	11	0	0
T2	8308	0	0	0
T3	23159	5	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	11	0	0
T11	0	11	0	0
T12	0	10	0	0
T14	0	32	0	0
T15	0	4	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	5	0	0
T20	1783	0	0	0
T23	0	3	0	0
T24	0	7	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	3104	0	0
T1	162161	11	0	0
T2	8303	0	0	0
T3	42743	5	0	0
T4	60410	0	0	0
T6	554	0	0	0
T9	0	11	0	0
T11	0	11	0	0
T12	0	10	0	0
T14	0	32	0	0
T15	0	4	0	0
T16	869	0	0	0
T17	4132	0	0	0
T18	1337	0	0	0
T19	29468	5	0	0
T20	952	0	0	0
T23	0	3	0	0
T24	0	7	0	0

Line Coverage for Instance : tb.dut.u_main_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T3,T19

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T19

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T3,T19
EVEN	0	-	Covered	T1,T3,T19
ODD	-	1	Covered	T1,T3,T19
ODD	-	0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T3,T19
EVEN	0	-	Covered	T1,T3,T19
ODD	-	1	Covered	T1,T3,T19
ODD	-	0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	166702677	3094	0	0
SyncReqAckHoldReq	431430169	3094	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	3094	0	0
T1	108652	4	0	0
T2	8308	0	0	0
T3	23159	7	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	24	0	0
T10	0	3	0	0
T11	0	10	0	0
T12	0	14	0	0
T14	0	24	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	9	0	0
T20	1783	0	0	0
T21	0	3	0	0
T24	0	4	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	3094	0	0
T1	694353	4	0	0
T2	34621	0	0	0
T3	178142	7	0	0
T4	245475	0	0	0
T6	2201	0	0	0
T9	0	24	0	0
T10	0	3	0	0
T11	0	10	0	0
T12	0	14	0	0
T14	0	24	0	0
T16	3733	0	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	9	0	0
T20	3638	0	0	0
T21	0	3	0	0
T24	0	4	0	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T3
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Covered	T1,T2,T3
ODD	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T3
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Covered	T1,T2,T3
ODD	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	166702677	2910	0	0
SyncReqAckHoldReq	207108858	2910	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	2910	0	0
T1	108652	15	0	0
T2	8308	4	0	0
T3	23159	3	0	0
T4	28322	0	0	0
T6	2135	0	0	0
T9	0	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	32	0	0
T15	0	4	0	0
T16	2426	0	0	0
T17	1510	0	0	0
T18	2348	0	0	0
T19	25806	0	0	0
T20	1783	0	0	0
T24	0	6	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108858	2910	0	0
T1	333295	15	0	0
T2	16618	4	0	0
T3	85509	3	0	0
T4	120709	0	0	0
T6	1056	0	0	0
T9	0	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	32	0	0
T15	0	4	0	0
T16	1791	0	0	0
T17	7254	0	0	0
T18	2348	0	0	0
T19	58985	0	0	0
T20	1746	0	0	0
T24	0	6	0	0