Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T1,T6
10CoveredT6,T4,T18
11CoveredT6,T4,T17

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 403443673 4212 0 0
g_div2.Div2Whole_A 403443673 4997 0 0
g_div4.Div4Stepped_A 200870614 4134 0 0
g_div4.Div4Whole_A 200870614 4733 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 403443673 4212 0 0
T2 33236 0 0 0
T3 171011 0 0 0
T4 241408 3 0 0
T6 2113 5 0 0
T9 0 30 0 0
T16 3585 0 0 0
T17 14509 9 0 0
T18 4695 11 0 0
T19 117965 0 0 0
T20 3493 9 0 0
T46 0 2 0 0
T48 0 2 0 0
T49 0 4 0 0
T102 4210 3 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 403443673 4997 0 0
T2 33236 0 0 0
T3 171011 0 0 0
T4 241408 3 0 0
T6 2113 5 0 0
T9 0 38 0 0
T16 3585 0 0 0
T17 14509 9 0 0
T18 4695 12 0 0
T19 117965 0 0 0
T20 3493 9 0 0
T46 0 2 0 0
T48 0 3 0 0
T49 0 8 0 0
T102 4210 4 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200870614 4134 0 0
T2 16606 0 0 0
T3 85487 0 0 0
T4 120822 3 0 0
T6 1111 5 0 0
T9 0 29 0 0
T16 1739 0 0 0
T17 8265 9 0 0
T18 2676 11 0 0
T19 58936 0 0 0
T20 1905 8 0 0
T46 0 1 0 0
T48 0 2 0 0
T49 0 2 0 0
T102 2204 3 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200870614 4733 0 0
T2 16606 0 0 0
T3 85487 0 0 0
T4 120822 3 0 0
T6 1111 5 0 0
T9 0 38 0 0
T16 1739 0 0 0
T17 8265 9 0 0
T18 2676 12 0 0
T19 58936 0 0 0
T20 1905 9 0 0
T46 0 1 0 0
T48 0 3 0 0
T49 0 7 0 0
T102 2204 4 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T1,T6
10CoveredT6,T4,T18
11CoveredT6,T4,T17

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 403443673 4212 0 0
g_div2.Div2Whole_A 403443673 4997 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 403443673 4212 0 0
T2 33236 0 0 0
T3 171011 0 0 0
T4 241408 3 0 0
T6 2113 5 0 0
T9 0 30 0 0
T16 3585 0 0 0
T17 14509 9 0 0
T18 4695 11 0 0
T19 117965 0 0 0
T20 3493 9 0 0
T46 0 2 0 0
T48 0 2 0 0
T49 0 4 0 0
T102 4210 3 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 403443673 4997 0 0
T2 33236 0 0 0
T3 171011 0 0 0
T4 241408 3 0 0
T6 2113 5 0 0
T9 0 38 0 0
T16 3585 0 0 0
T17 14509 9 0 0
T18 4695 12 0 0
T19 117965 0 0 0
T20 3493 9 0 0
T46 0 2 0 0
T48 0 3 0 0
T49 0 8 0 0
T102 4210 4 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T1,T6
10CoveredT6,T4,T18
11CoveredT6,T4,T17

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 200870614 4134 0 0
g_div4.Div4Whole_A 200870614 4733 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200870614 4134 0 0
T2 16606 0 0 0
T3 85487 0 0 0
T4 120822 3 0 0
T6 1111 5 0 0
T9 0 29 0 0
T16 1739 0 0 0
T17 8265 9 0 0
T18 2676 11 0 0
T19 58936 0 0 0
T20 1905 8 0 0
T46 0 1 0 0
T48 0 2 0 0
T49 0 2 0 0
T102 2204 3 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200870614 4733 0 0
T2 16606 0 0 0
T3 85487 0 0 0
T4 120822 3 0 0
T6 1111 5 0 0
T9 0 38 0 0
T16 1739 0 0 0
T17 8265 9 0 0
T18 2676 12 0 0
T19 58936 0 0 0
T20 1905 9 0 0
T46 0 1 0 0
T48 0 3 0 0
T49 0 7 0 0
T102 2204 4 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%