Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	500108031	420	0	0
StatusRise_A	500108031	420	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500108031	420	0	0
T10	56796	0	0	0
T36	4227	7	0	0
T37	3561	7	0	0
T38	0	6	0	0
T40	45564	0	0	0
T45	2553	0	0	0
T46	4884	0	0	0
T47	3078	0	0	0
T48	5097	0	0	0
T49	5958	0	0	0
T69	7389	0	0	0
T147	0	16	0	0
T148	0	15	0	0
T149	0	8	0	0
T150	0	6	0	0
T151	0	7	0	0
T152	0	5	0	0
T153	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500108031	420	0	0
T10	56796	0	0	0
T36	4227	7	0	0
T37	3561	7	0	0
T38	0	6	0	0
T40	45564	0	0	0
T45	2553	0	0	0
T46	4884	0	0	0
T47	3078	0	0	0
T48	5097	0	0	0
T49	5958	0	0	0
T69	7389	0	0	0
T147	0	16	0	0
T148	0	15	0	0
T149	0	8	0	0
T150	0	6	0	0
T151	0	7	0	0
T152	0	5	0	0
T153	0	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	166702677	145	0	0
StatusRise_A	166702677	145	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	145	0	0
T10	18932	0	0	0
T36	1409	2	0	0
T37	1187	2	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T48	1699	0	0	0
T49	1986	0	0	0
T69	2463	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	145	0	0
T10	18932	0	0	0
T36	1409	2	0	0
T37	1187	2	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T48	1699	0	0	0
T49	1986	0	0	0
T69	2463	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	166702677	136	0	0
StatusRise_A	166702677	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	136	0	0
T10	18932	0	0	0
T36	1409	2	0	0
T37	1187	3	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T48	1699	0	0	0
T49	1986	0	0	0
T69	2463	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0
T152	0	1	0	0
T153	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	136	0	0
T10	18932	0	0	0
T36	1409	2	0	0
T37	1187	3	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T48	1699	0	0	0
T49	1986	0	0	0
T69	2463	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0
T152	0	1	0	0
T153	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	166702677	139	0	0
StatusRise_A	166702677	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	139	0	0
T10	18932	0	0	0
T36	1409	3	0	0
T37	1187	2	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T48	1699	0	0	0
T49	1986	0	0	0
T69	2463	0	0	0
T147	0	6	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166702677	139	0	0
T10	18932	0	0	0
T36	1409	3	0	0
T37	1187	2	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	851	0	0	0
T46	1628	0	0	0
T47	1026	0	0	0
T48	1699	0	0	0
T49	1986	0	0	0
T69	2463	0	0	0
T147	0	6	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0