Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51086	0	0
CgEnOn_A	2147483647	41753	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51086	0	0
T1	2524466	257	0	0
T2	127385	3	0	0
T3	655523	3	0	0
T4	913589	154	0	0
T5	82536	8	0	0
T6	8179	3	0	0
T9	1687722	49	0	0
T10	142347	0	0	0
T16	13657	5	0	0
T17	57133	3	0	0
T18	18489	3	0	0
T19	452135	3	0	0
T29	14973	0	0	0
T36	4205	12	0	0
T37	7319	17	0	0
T38	0	10	0	0
T39	0	5	0	0
T40	42809	0	0	0
T41	0	1	0	0
T45	24400	0	0	0
T46	5374	0	0	0
T47	13349	0	0	0
T48	1771	0	0	0
T69	30973	0	0	0
T147	0	25	0	0
T148	0	25	0	0
T149	0	15	0	0
T150	0	15	0	0
T151	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41753	0	0
T1	486482	233	0	0
T2	24908	0	0	0
T3	128229	0	0	0
T4	181231	130	0	0
T5	0	5	0	0
T6	1664	0	0	0
T9	1562417	263	0	0
T10	97268	0	0	0
T16	2607	2	0	0
T17	12396	0	0	0
T18	4013	0	0	0
T19	88404	0	0	0
T20	2856	0	0	0
T21	0	5	0	0
T29	8251	0	0	0
T36	2875	18	0	0
T37	4982	26	0	0
T38	0	10	0	0
T39	0	5	0	0
T40	27621	0	0	0
T41	0	3	0	0
T45	16663	5	0	0
T46	3677	0	0	0
T47	9072	29	0	0
T48	1699	0	0	0
T69	21119	0	0	0
T147	0	25	0	0
T148	0	25	0	0
T149	0	15	0	0
T150	0	15	0	0
T151	0	15	0	0
T152	0	1	0	0
T154	0	5	0	0
T155	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	200870208	149	0	0
CgEnOn_A	200870208	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200870208	149	0	0
T9	624974	1	0	0
T10	21597	0	0	0
T29	3301	0	0	0
T36	627	2	0	0
T37	1087	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	5223	0	0	0
T45	3695	0	0	0
T46	819	0	0	0
T47	1986	0	0	0
T69	4663	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200870208	149	0	0
T9	624974	1	0	0
T10	21597	0	0	0
T29	3301	0	0	0
T36	627	2	0	0
T37	1087	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	5223	0	0	0
T45	3695	0	0	0
T46	819	0	0	0
T47	1986	0	0	0
T69	4663	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	100434511	149	0	0
CgEnOn_A	100434511	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	149	0	0
T9	312481	1	0	0
T10	10799	0	0	0
T29	1650	0	0	0
T36	314	2	0	0
T37	543	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2606	0	0	0
T45	1847	0	0	0
T46	410	0	0	0
T47	993	0	0	0
T69	2332	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	149	0	0
T9	312481	1	0	0
T10	10799	0	0	0
T29	1650	0	0	0
T36	314	2	0	0
T37	543	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2606	0	0	0
T45	1847	0	0	0
T46	410	0	0	0
T47	993	0	0	0
T69	2332	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	100434511	149	0	0
CgEnOn_A	100434511	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	149	0	0
T9	312481	1	0	0
T10	10799	0	0	0
T29	1650	0	0	0
T36	314	2	0	0
T37	543	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2606	0	0	0
T45	1847	0	0	0
T46	410	0	0	0
T47	993	0	0	0
T69	2332	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	149	0	0
T9	312481	1	0	0
T10	10799	0	0	0
T29	1650	0	0	0
T36	314	2	0	0
T37	543	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2606	0	0	0
T45	1847	0	0	0
T46	410	0	0	0
T47	993	0	0	0
T69	2332	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	100434511	149	0	0
CgEnOn_A	100434511	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	149	0	0
T9	312481	1	0	0
T10	10799	0	0	0
T29	1650	0	0	0
T36	314	2	0	0
T37	543	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2606	0	0	0
T45	1847	0	0	0
T46	410	0	0	0
T47	993	0	0	0
T69	2332	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	149	0	0
T9	312481	1	0	0
T10	10799	0	0	0
T29	1650	0	0	0
T36	314	2	0	0
T37	543	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	2606	0	0	0
T45	1847	0	0	0
T46	410	0	0	0
T47	993	0	0	0
T69	2332	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	403443252	149	0	0
CgEnOn_A	403443252	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403443252	149	0	0
T9	125305	1	0	0
T10	43274	0	0	0
T29	6722	0	0	0
T36	1306	2	0	0
T37	2266	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	14580	0	0	0
T45	7427	0	0	0
T46	1628	0	0	0
T47	4107	0	0	0
T69	9460	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403443252	138	0	0
T10	43274	0	0	0
T36	1306	2	0	0
T37	2266	3	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	14580	0	0	0
T45	7427	0	0	0
T46	1628	0	0	0
T47	4107	0	0	0
T48	1699	0	0	0
T49	1907	0	0	0
T69	9460	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	3	0	0
T152	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	431430169	151	0	0
CgEnOn_A	431430169	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	151	0	0
T10	45079	0	0	0
T11	0	1	0	0
T36	1330	2	0	0
T37	2337	2	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	7737	0	0	0
T46	1697	0	0	0
T47	4277	0	0	0
T48	1771	0	0	0
T49	1986	0	0	0
T69	9854	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	146	0	0
T10	45079	0	0	0
T36	1330	2	0	0
T37	2337	2	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	7737	0	0	0
T46	1697	0	0	0
T47	4277	0	0	0
T48	1771	0	0	0
T49	1986	0	0	0
T69	9854	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	431430169	151	0	0
CgEnOn_A	431430169	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	151	0	0
T10	45079	0	0	0
T11	0	1	0	0
T36	1330	2	0	0
T37	2337	2	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	7737	0	0	0
T46	1697	0	0	0
T47	4277	0	0	0
T48	1771	0	0	0
T49	1986	0	0	0
T69	9854	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	146	0	0
T10	45079	0	0	0
T36	1330	2	0	0
T37	2337	2	0	0
T38	0	2	0	0
T40	15188	0	0	0
T45	7737	0	0	0
T46	1697	0	0	0
T47	4277	0	0	0
T48	1771	0	0	0
T49	1986	0	0	0
T69	9854	0	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207108858	141	0	0
CgEnOn_A	207108858	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108858	141	0	0
T10	21638	0	0	0
T36	658	3	0	0
T37	1161	2	0	0
T38	0	2	0	0
T40	7291	0	0	0
T45	3714	0	0	0
T46	814	0	0	0
T47	2053	0	0	0
T48	850	0	0	0
T49	953	0	0	0
T69	4730	0	0	0
T147	0	6	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108858	140	0	0
T10	21638	0	0	0
T36	658	3	0	0
T37	1161	2	0	0
T38	0	2	0	0
T40	7291	0	0	0
T45	3714	0	0	0
T46	814	0	0	0
T47	2053	0	0	0
T48	850	0	0	0
T49	953	0	0	0
T69	4730	0	0	0
T147	0	6	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	100434511	8088	0	0
CgEnOn_A	100434511	5771	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	8088	0	0
T1	162161	78	0	0
T2	8303	1	0	0
T3	42743	1	0	0
T4	60410	40	0	0
T5	5372	1	0	0
T6	554	1	0	0
T16	869	1	0	0
T17	4132	1	0	0
T18	1337	1	0	0
T19	29468	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100434511	5771	0	0
T1	162161	70	0	0
T2	8303	0	0	0
T3	42743	0	0	0
T4	60410	32	0	0
T6	554	0	0	0
T9	0	71	0	0
T16	869	0	0	0
T17	4132	0	0	0
T18	1337	0	0	0
T19	29468	0	0	0
T20	952	0	0	0
T21	0	1	0	0
T36	0	2	0	0
T37	0	3	0	0
T45	0	2	0	0
T47	0	11	0	0
T154	0	2	0	0
T155	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	200870208	8232	0	0
CgEnOn_A	200870208	5915	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200870208	8232	0	0
T1	324321	78	0	0
T2	16605	1	0	0
T3	85486	1	0	0
T4	120821	41	0	0
T5	10745	1	0	0
T6	1110	1	0	0
T16	1738	1	0	0
T17	8264	1	0	0
T18	2676	1	0	0
T19	58936	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200870208	5915	0	0
T1	324321	70	0	0
T2	16605	0	0	0
T3	85486	0	0	0
T4	120821	33	0	0
T6	1110	0	0	0
T9	0	74	0	0
T16	1738	0	0	0
T17	8264	0	0	0
T18	2676	0	0	0
T19	58936	0	0	0
T20	1904	0	0	0
T21	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T41	0	1	0	0
T45	0	2	0	0
T47	0	10	0	0
T154	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	403443252	8185	0	0
CgEnOn_A	403443252	5857	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403443252	8185	0	0
T1	649278	77	0	0
T2	33235	1	0	0
T3	171010	1	0	0
T4	241408	36	0	0
T5	21541	1	0	0
T6	2113	1	0	0
T16	3584	1	0	0
T17	14509	1	0	0
T18	4694	1	0	0
T19	117965	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403443252	5857	0	0
T1	649278	69	0	0
T2	33235	0	0	0
T3	171010	0	0	0
T4	241408	28	0	0
T6	2113	0	0	0
T9	0	70	0	0
T16	3584	0	0	0
T17	14509	0	0	0
T18	4694	0	0	0
T19	117965	0	0	0
T20	3493	0	0	0
T21	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T41	0	1	0	0
T45	0	1	0	0
T47	0	8	0	0
T154	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207108858	8196	0	0
CgEnOn_A	207108858	5867	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108858	8196	0	0
T1	333295	80	0	0
T2	16618	1	0	0
T3	85509	1	0	0
T4	120709	37	0	0
T5	10771	1	0	0
T6	1056	1	0	0
T16	1791	1	0	0
T17	7254	1	0	0
T18	2348	1	0	0
T19	58985	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108858	5867	0	0
T1	333295	72	0	0
T2	16618	0	0	0
T3	85509	0	0	0
T4	120709	29	0	0
T6	1056	0	0	0
T9	0	68	0	0
T16	1791	0	0	0
T17	7254	0	0	0
T18	2348	0	0	0
T19	58985	0	0	0
T20	1746	0	0	0
T21	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T45	0	2	0	0
T47	0	10	0	0
T154	0	2	0	0
T155	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T16
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	431430169	4321	0	0
CgEnOn_A	431430169	4316	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	4321	0	0
T1	694353	24	0	0
T2	34621	0	0	0
T3	178142	0	0	0
T4	245475	37	0	0
T5	22439	5	0	0
T6	2201	0	0	0
T9	0	44	0	0
T16	3733	2	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	4316	0	0
T1	694353	24	0	0
T2	34621	0	0	0
T3	178142	0	0	0
T4	245475	37	0	0
T5	22439	5	0	0
T6	2201	0	0	0
T9	0	44	0	0
T16	3733	2	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T16
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	431430169	4298	0	0
CgEnOn_A	431430169	4293	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	4298	0	0
T1	694353	25	0	0
T2	34621	0	0	0
T3	178142	0	0	0
T4	245475	33	0	0
T5	22439	2	0	0
T6	2201	0	0	0
T9	0	53	0	0
T16	3733	6	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T41	0	1	0	0
T51	0	2	0	0
T69	0	12	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	4293	0	0
T1	694353	25	0	0
T2	34621	0	0	0
T3	178142	0	0	0
T4	245475	33	0	0
T5	22439	2	0	0
T6	2201	0	0	0
T9	0	53	0	0
T16	3733	6	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T41	0	1	0	0
T51	0	2	0	0
T69	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T16
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	431430169	4308	0	0
CgEnOn_A	431430169	4303	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	4308	0	0
T1	694353	25	0	0
T2	34621	0	0	0
T3	178142	0	0	0
T4	245475	40	0	0
T5	22439	4	0	0
T6	2201	0	0	0
T9	0	49	0	0
T16	3733	7	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	4303	0	0
T1	694353	25	0	0
T2	34621	0	0	0
T3	178142	0	0	0
T4	245475	40	0	0
T5	22439	4	0	0
T6	2201	0	0	0
T9	0	49	0	0
T16	3733	7	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T9
1	0	Covered	T5,T1,T16
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	431430169	4270	0	0
CgEnOn_A	431430169	4265	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	4270	0	0
T1	694353	28	0	0
T2	34621	0	0	0
T3	178142	0	0	0
T4	245475	42	0	0
T5	22439	6	0	0
T6	2201	0	0	0
T9	0	49	0	0
T16	3733	4	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431430169	4265	0	0
T1	694353	28	0	0
T2	34621	0	0	0
T3	178142	0	0	0
T4	245475	42	0	0
T5	22439	6	0	0
T6	2201	0	0	0
T9	0	49	0	0
T16	3733	4	0	0
T17	15114	0	0	0
T18	4891	0	0	0
T19	122883	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T41	0	1	0	0
T51	0	1	0	0
T69	0	11	0	0