Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	651488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3869148

1

T6

3

T1

15164

T7

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1113735	1			T1	4289		T7	27		T4	17
values[0x0]	1561842	1			T6	8		T1	6351		T7	19
values[0x1]	1845059	1			T6	5		T1	7373		T7	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	353285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4167351

1

T6

4

T1

16404

T7

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17675	1			T1	73		T18	1		T2	2
valid_sources[0x01]	16405	1			T1	66		T4	6		T110	1
valid_sources[0x02]	18279	1			T1	66		T4	4		T3	2
valid_sources[0x03]	15506	1			T1	64		T4	2		T110	1
valid_sources[0x04]	17868	1			T1	56		T4	1		T2	1
valid_sources[0x05]	16904	1			T1	85		T110	1		T3	2
valid_sources[0x06]	17548	1			T1	77		T7	1		T4	1
valid_sources[0x07]	16847	1			T1	77		T18	2		T2	1
valid_sources[0x08]	17962	1			T1	69		T5	9		T18	4
valid_sources[0x09]	17250	1			T1	80		T4	8		T18	3
valid_sources[0x0a]	15100	1			T1	80		T4	4		T2	1
valid_sources[0x0b]	19322	1			T1	73		T4	4		T2	2
valid_sources[0x0c]	16939	1			T1	62		T4	2		T2	2
valid_sources[0x0d]	18858	1			T1	63		T71	2		T110	1
valid_sources[0x0e]	17366	1			T1	88		T4	7		T18	1
valid_sources[0x0f]	17163	1			T1	49		T4	1		T18	1
valid_sources[0x10]	19264	1			T1	73		T110	1		T24	7
valid_sources[0x11]	18652	1			T1	66		T5	2		T110	1
valid_sources[0x12]	17964	1			T1	62		T18	3		T2	1
valid_sources[0x13]	18262	1			T1	76		T4	2		T18	4
valid_sources[0x14]	18718	1			T1	78		T4	5		T2	1
valid_sources[0x15]	16351	1			T1	60		T9	1		T26	2
valid_sources[0x16]	19468	1			T1	61		T18	2		T2	1
valid_sources[0x17]	18313	1			T1	74		T18	3		T2	5
valid_sources[0x18]	16732	1			T1	60		T7	1		T18	2
valid_sources[0x19]	17257	1			T1	71		T4	1		T2	1
valid_sources[0x1a]	16588	1			T1	74		T4	1		T2	1
valid_sources[0x1b]	17255	1			T1	63		T4	1		T18	1
valid_sources[0x1c]	18938	1			T1	78		T2	2		T110	2
valid_sources[0x1d]	17312	1			T1	60		T2	1		T3	3
valid_sources[0x1e]	16629	1			T1	61		T2	1		T110	2
valid_sources[0x1f]	17861	1			T1	63		T18	6		T2	1
valid_sources[0x20]	16494	1			T1	77		T4	3		T5	4
valid_sources[0x21]	17732	1			T1	63		T4	2		T3	2
valid_sources[0x22]	16903	1			T1	84		T4	10		T18	2
valid_sources[0x23]	18727	1			T1	79		T5	1		T18	2
valid_sources[0x24]	18590	1			T1	64		T16	1		T2	1
valid_sources[0x25]	18165	1			T1	77		T110	2		T3	4
valid_sources[0x26]	16945	1			T1	84		T5	4		T2	1
valid_sources[0x27]	17996	1			T1	81		T18	1		T2	2
valid_sources[0x28]	18107	1			T1	78		T4	1		T110	3
valid_sources[0x29]	17143	1			T1	72		T4	1		T16	11
valid_sources[0x2a]	17924	1			T1	62		T110	1		T3	6
valid_sources[0x2b]	17399	1			T1	62		T2	2		T3	3
valid_sources[0x2c]	17387	1			T1	76		T4	6		T110	1
valid_sources[0x2d]	16222	1			T1	61		T26	2		T150	1
valid_sources[0x2e]	19098	1			T1	69		T4	1		T2	1
valid_sources[0x2f]	17548	1			T1	56		T4	6		T18	2
valid_sources[0x30]	18097	1			T1	82		T4	1		T18	1
valid_sources[0x31]	16673	1			T6	13		T1	62		T2	1
valid_sources[0x32]	18361	1			T1	72		T4	3		T2	2
valid_sources[0x33]	19511	1			T1	54		T4	2		T5	1
valid_sources[0x34]	15033	1			T1	75		T4	2		T110	2
valid_sources[0x35]	18544	1			T1	86		T111	1		T112	1
valid_sources[0x36]	17616	1			T1	58		T110	2		T3	4
valid_sources[0x37]	17234	1			T1	66		T2	1		T3	1
valid_sources[0x38]	18494	1			T1	74		T18	3		T3	1
valid_sources[0x39]	17009	1			T1	66		T18	1		T2	1
valid_sources[0x3a]	17937	1			T1	57		T4	1		T2	1
valid_sources[0x3b]	17710	1			T1	76		T4	2		T5	2
valid_sources[0x3c]	17679	1			T1	68		T5	2		T17	1
valid_sources[0x3d]	16710	1			T1	75		T4	4		T5	6
valid_sources[0x3e]	17494	1			T1	79		T5	8		T106	5
valid_sources[0x3f]	17991	1			T1	79		T4	1		T5	5
valid_sources[0x40]	17825	1			T1	60		T4	3		T5	8
valid_sources[0x41]	16761	1			T1	74		T2	1		T25	1
valid_sources[0x42]	17032	1			T1	67		T18	3		T2	2
valid_sources[0x43]	17199	1			T1	62		T4	1		T2	2
valid_sources[0x44]	17150	1			T1	70		T16	22		T3	5
valid_sources[0x45]	18564	1			T1	81		T18	2		T2	1
valid_sources[0x46]	19025	1			T1	59		T7	24		T4	6
valid_sources[0x47]	16641	1			T1	57		T3	3		T25	3
valid_sources[0x48]	17009	1			T1	79		T18	4		T3	2
valid_sources[0x49]	17150	1			T1	60		T2	2		T3	1
valid_sources[0x4a]	18787	1			T1	59		T5	5		T2	1
valid_sources[0x4b]	17072	1			T1	72		T4	8		T18	4
valid_sources[0x4c]	16498	1			T1	68		T4	3		T2	1
valid_sources[0x4d]	17638	1			T1	82		T4	10		T3	2
valid_sources[0x4e]	16820	1			T1	72		T7	1		T18	4
valid_sources[0x4f]	17780	1			T1	78		T4	3		T16	5
valid_sources[0x50]	17354	1			T1	63		T5	10		T18	4
valid_sources[0x51]	16981	1			T1	78		T4	1		T18	1
valid_sources[0x52]	18113	1			T1	61		T4	1		T5	4
valid_sources[0x53]	21917	1			T1	75		T4	3		T5	8
valid_sources[0x54]	19219	1			T1	62		T17	1		T18	1
valid_sources[0x55]	19316	1			T1	70		T4	1		T18	7
valid_sources[0x56]	17537	1			T1	62		T4	1		T110	2
valid_sources[0x57]	17181	1			T1	80		T18	1		T110	1
valid_sources[0x58]	16340	1			T1	71		T18	4		T110	1
valid_sources[0x59]	17610	1			T1	72		T110	1		T3	2
valid_sources[0x5a]	17182	1			T1	71		T5	3		T2	1
valid_sources[0x5b]	16787	1			T1	69		T106	1		T131	1
valid_sources[0x5c]	17635	1			T1	73		T4	2		T2	1
valid_sources[0x5d]	18111	1			T1	70		T4	1		T3	1
valid_sources[0x5e]	17361	1			T1	58		T7	6		T2	1
valid_sources[0x5f]	19218	1			T1	80		T4	1		T18	6
valid_sources[0x60]	18944	1			T1	70		T4	2		T18	1
valid_sources[0x61]	18148	1			T1	65		T18	5		T110	1
valid_sources[0x62]	17875	1			T1	77		T4	1		T2	1
valid_sources[0x63]	17999	1			T1	77		T4	4		T2	1
valid_sources[0x64]	17893	1			T1	82		T3	3		T25	1
valid_sources[0x65]	17686	1			T1	61		T2	1		T9	2
valid_sources[0x66]	17311	1			T1	62		T4	1		T18	3
valid_sources[0x67]	18597	1			T1	63		T5	1		T2	2
valid_sources[0x68]	17709	1			T1	72		T4	1		T18	4
valid_sources[0x69]	18355	1			T1	71		T4	3		T18	2
valid_sources[0x6a]	17460	1			T1	68		T3	4		T9	2
valid_sources[0x6b]	19320	1			T1	62		T18	4		T2	2
valid_sources[0x6c]	17616	1			T1	66		T2	1		T110	4
valid_sources[0x6d]	17076	1			T1	66		T4	5		T110	1
valid_sources[0x6e]	17742	1			T1	79		T4	1		T17	1
valid_sources[0x6f]	18155	1			T1	67		T4	6		T18	4
valid_sources[0x70]	18467	1			T1	62		T2	1		T110	1
valid_sources[0x71]	17706	1			T1	66		T3	3		T94	1
valid_sources[0x72]	16806	1			T1	71		T4	1		T110	1
valid_sources[0x73]	16408	1			T1	83		T4	7		T2	1
valid_sources[0x74]	16406	1			T1	58		T7	1		T4	1
valid_sources[0x75]	16725	1			T1	69		T5	1		T2	1
valid_sources[0x76]	16944	1			T1	56		T2	1		T3	2
valid_sources[0x77]	17372	1			T1	61		T7	1		T4	5
valid_sources[0x78]	17525	1			T1	71		T5	1		T2	2
valid_sources[0x79]	16086	1			T1	64		T5	1		T110	1
valid_sources[0x7a]	18176	1			T1	88		T4	2		T18	1
valid_sources[0x7b]	17292	1			T1	83		T110	1		T94	1
valid_sources[0x7c]	16837	1			T1	62		T17	1		T82	6
valid_sources[0x7d]	17481	1			T1	64		T4	6		T3	1
valid_sources[0x7e]	17918	1			T1	87		T3	2		T111	1
valid_sources[0x7f]	16701	1			T1	74		T110	1		T3	1
valid_sources[0x80]	17240	1			T1	67		T110	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

978416

1

T1

3758

T7

17

T4

8

values[0x0]

all_enables

biggest_size

1466981

1

T6

1

T1

5868

T7

8

values[0x1]

all_enables

biggest_size

1423751

1

T6

2

T1

5538

T7

1