Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T18
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1335471402	13684	0	0
GateOpen_A	1335471402	20324	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335471402	13684	0	0
T1	1133225	143	0	0
T2	253681	0	0	0
T3	0	8	0	0
T4	358376	0	0	0
T5	204737	0	0	0
T6	7261	15	0	0
T7	6354	0	0	0
T16	95896	0	0	0
T17	36087	0	0	0
T18	60680	64	0	0
T19	18802	0	0	0
T20	0	4	0	0
T34	0	16	0	0
T35	0	19	0	0
T113	0	4	0	0
T131	0	4	0	0
T177	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1335471402	20324	0	0
T1	1133225	155	0	0
T2	253681	4	0	0
T4	358376	4	0	0
T5	204737	4	0	0
T6	7261	15	0	0
T7	6354	0	0	0
T16	95896	0	0	0
T17	36087	4	0	0
T18	60680	72	0	0
T19	18802	0	0	0
T20	0	8	0	0
T28	0	4	0	0
T71	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T18
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	148347861	3238	0	0
GateOpen_A	148347861	4898	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347861	3238	0	0
T1	626530	36	0	0
T2	28169	0	0	0
T3	0	2	0	0
T4	37877	0	0	0
T5	22100	0	0	0
T6	785	3	0	0
T7	944	0	0	0
T16	12315	0	0	0
T17	4250	0	0	0
T18	6953	15	0	0
T19	2072	0	0	0
T20	0	1	0	0
T34	0	4	0	0
T35	0	4	0	0
T113	0	1	0	0
T131	0	1	0	0
T177	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347861	4898	0	0
T1	626530	39	0	0
T2	28169	1	0	0
T4	37877	1	0	0
T5	22100	1	0	0
T6	785	3	0	0
T7	944	0	0	0
T16	12315	0	0	0
T17	4250	1	0	0
T18	6953	17	0	0
T19	2072	0	0	0
T20	0	2	0	0
T28	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T18
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	296696432	3498	0	0
GateOpen_A	296696432	5158	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296696432	3498	0	0
T1	125306	38	0	0
T2	56337	0	0	0
T3	0	2	0	0
T4	75753	0	0	0
T5	44199	0	0	0
T6	1569	3	0	0
T7	1890	0	0	0
T16	24630	0	0	0
T17	8501	0	0	0
T18	13907	16	0	0
T19	4143	0	0	0
T20	0	1	0	0
T34	0	4	0	0
T35	0	4	0	0
T113	0	1	0	0
T131	0	1	0	0
T177	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296696432	5158	0	0
T1	125306	41	0	0
T2	56337	1	0	0
T4	75753	1	0	0
T5	44199	1	0	0
T6	1569	3	0	0
T7	1890	0	0	0
T16	24630	0	0	0
T17	8501	1	0	0
T18	13907	18	0	0
T19	4143	0	0	0
T20	0	2	0	0
T28	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T18
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	590418673	3462	0	0
GateOpen_A	590418673	5122	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590418673	3462	0	0
T1	250862	34	0	0
T2	112781	0	0	0
T3	0	2	0	0
T4	151641	0	0	0
T5	88450	0	0	0
T6	3271	4	0	0
T7	2347	0	0	0
T16	39300	0	0	0
T17	15557	0	0	0
T18	26546	16	0	0
T19	8391	0	0	0
T20	0	1	0	0
T34	0	4	0	0
T35	0	4	0	0
T113	0	1	0	0
T131	0	1	0	0
T177	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590418673	5122	0	0
T1	250862	37	0	0
T2	112781	1	0	0
T4	151641	1	0	0
T5	88450	1	0	0
T6	3271	4	0	0
T7	2347	0	0	0
T16	39300	0	0	0
T17	15557	1	0	0
T18	26546	18	0	0
T19	8391	0	0	0
T20	0	2	0	0
T28	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T18
0	1	Covered	T6,T1,T18
1	0	Covered	T6,T1,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T18
1	0	Covered	T34,T35,T36
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	300008436	3486	0	0
GateOpen_A	300008436	5146	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300008436	3486	0	0
T1	130527	35	0	0
T2	56394	0	0	0
T3	0	2	0	0
T4	93105	0	0	0
T5	49988	0	0	0
T6	1636	5	0	0
T7	1173	0	0	0
T16	19651	0	0	0
T17	7779	0	0	0
T18	13274	17	0	0
T19	4196	0	0	0
T20	0	1	0	0
T34	0	4	0	0
T35	0	7	0	0
T113	0	1	0	0
T131	0	1	0	0
T177	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300008436	5146	0	0
T1	130527	38	0	0
T2	56394	1	0	0
T4	93105	1	0	0
T5	49988	1	0	0
T6	1636	5	0	0
T7	1173	0	0	0
T16	19651	0	0	0
T17	7779	1	0	0
T18	13274	19	0	0
T19	4196	0	0	0
T20	0	2	0	0
T28	0	1	0	0
T71	0	1	0	0