Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	800553470	69685	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	800553470	69685	0	0
T1	3272650	129	0	0
T2	217345	49	0	0
T3	0	144	0	0
T4	473720	0	0	0
T5	604590	0	0	0
T7	11730	0	0	0
T9	0	37	0	0
T10	0	111	0	0
T11	0	148	0	0
T12	0	446	0	0
T13	0	1456	0	0
T14	0	1287	0	0
T15	0	205	0	0
T16	10230	0	0	0
T17	4045	0	0	0
T18	34560	0	0	0
T19	10920	0	0	0
T20	7525	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160110694	10403	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	10403	0	0
T1	654530	20	0	0
T2	43469	8	0	0
T3	0	23	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	0	0	0
T9	0	7	0	0
T10	0	16	0	0
T11	0	24	0	0
T12	0	57	0	0
T13	0	232	0	0
T14	0	207	0	0
T15	0	29	0	0
T16	2046	0	0	0
T17	809	0	0	0
T18	6912	0	0	0
T19	2184	0	0	0
T20	1505	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160110694	10383	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	10383	0	0
T1	654530	20	0	0
T2	43469	8	0	0
T3	0	23	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	0	0	0
T9	0	7	0	0
T10	0	14	0	0
T11	0	24	0	0
T12	0	64	0	0
T13	0	230	0	0
T14	0	202	0	0
T15	0	29	0	0
T16	2046	0	0	0
T17	809	0	0	0
T18	6912	0	0	0
T19	2184	0	0	0
T20	1505	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160110694	13973	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	13973	0	0
T1	654530	26	0	0
T2	43469	10	0	0
T3	0	29	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	0	0	0
T9	0	7	0	0
T10	0	22	0	0
T11	0	30	0	0
T12	0	89	0	0
T13	0	294	0	0
T14	0	259	0	0
T15	0	46	0	0
T16	2046	0	0	0
T17	809	0	0	0
T18	6912	0	0	0
T19	2184	0	0	0
T20	1505	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160110694	13970	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	13970	0	0
T1	654530	26	0	0
T2	43469	9	0	0
T3	0	30	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	0	0	0
T9	0	7	0	0
T10	0	22	0	0
T11	0	30	0	0
T12	0	90	0	0
T13	0	294	0	0
T14	0	260	0	0
T15	0	40	0	0
T16	2046	0	0	0
T17	809	0	0	0
T18	6912	0	0	0
T19	2184	0	0	0
T20	1505	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	160110694	20956	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	20956	0	0
T1	654530	37	0	0
T2	43469	14	0	0
T3	0	39	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	0	0	0
T9	0	9	0	0
T10	0	37	0	0
T11	0	40	0	0
T12	0	146	0	0
T13	0	406	0	0
T14	0	359	0	0
T15	0	61	0	0
T16	2046	0	0	0
T17	809	0	0	0
T18	6912	0	0	0
T19	2184	0	0	0
T20	1505	0	0	0