Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
12985814 |
12936824 |
0 |
0 |
T2 |
2032380 |
2029116 |
0 |
0 |
T4 |
3528105 |
3524295 |
0 |
0 |
T5 |
3031287 |
3027624 |
0 |
0 |
T6 |
52628 |
49505 |
0 |
0 |
T7 |
63547 |
60522 |
0 |
0 |
T16 |
532291 |
529979 |
0 |
0 |
T17 |
208813 |
207754 |
0 |
0 |
T18 |
432859 |
423462 |
0 |
0 |
T19 |
136445 |
133895 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
960664164 |
946539108 |
0 |
14490 |
T1 |
3927180 |
3910974 |
0 |
18 |
T2 |
260814 |
260328 |
0 |
18 |
T4 |
568464 |
567828 |
0 |
18 |
T5 |
725508 |
724572 |
0 |
18 |
T6 |
4902 |
4560 |
0 |
18 |
T7 |
14076 |
13332 |
0 |
18 |
T16 |
12276 |
12198 |
0 |
18 |
T17 |
4854 |
4812 |
0 |
18 |
T18 |
41472 |
40368 |
0 |
18 |
T19 |
13104 |
12816 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
2643614 |
2632657 |
0 |
21 |
T2 |
669654 |
668426 |
0 |
21 |
T4 |
1092984 |
1091636 |
0 |
21 |
T5 |
794841 |
793746 |
0 |
21 |
T6 |
18532 |
17282 |
0 |
21 |
T7 |
16818 |
15930 |
0 |
21 |
T16 |
207148 |
206056 |
0 |
21 |
T17 |
81995 |
81484 |
0 |
21 |
T18 |
150977 |
147083 |
0 |
21 |
T19 |
47727 |
46705 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
188967 |
0 |
0 |
T1 |
2643614 |
1495 |
0 |
0 |
T2 |
669654 |
4 |
0 |
0 |
T4 |
1092984 |
4 |
0 |
0 |
T5 |
794841 |
4 |
0 |
0 |
T6 |
13628 |
22 |
0 |
0 |
T7 |
16818 |
176 |
0 |
0 |
T16 |
207148 |
192 |
0 |
0 |
T17 |
81995 |
42 |
0 |
0 |
T18 |
150977 |
495 |
0 |
0 |
T19 |
47727 |
123 |
0 |
0 |
T20 |
4635 |
0 |
0 |
0 |
T71 |
0 |
52 |
0 |
0 |
T82 |
0 |
143 |
0 |
0 |
T106 |
0 |
119 |
0 |
0 |
T107 |
0 |
100 |
0 |
0 |
T109 |
0 |
20 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
6415020 |
6393040 |
0 |
0 |
T2 |
1101912 |
1100323 |
0 |
0 |
T4 |
1866657 |
1864792 |
0 |
0 |
T5 |
1510938 |
1509267 |
0 |
0 |
T6 |
29194 |
27624 |
0 |
0 |
T7 |
32653 |
31221 |
0 |
0 |
T16 |
312867 |
311686 |
0 |
0 |
T17 |
121964 |
121419 |
0 |
0 |
T18 |
240410 |
235855 |
0 |
0 |
T19 |
75614 |
74335 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
590418230 |
586282343 |
0 |
0 |
T1 |
250862 |
249788 |
0 |
0 |
T2 |
112780 |
112577 |
0 |
0 |
T4 |
151640 |
151423 |
0 |
0 |
T5 |
88449 |
88301 |
0 |
0 |
T6 |
3270 |
3053 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
39300 |
39097 |
0 |
0 |
T17 |
15557 |
15463 |
0 |
0 |
T18 |
26545 |
25875 |
0 |
0 |
T19 |
8391 |
8216 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
590418230 |
586275353 |
0 |
2415 |
T1 |
250862 |
249787 |
0 |
3 |
T2 |
112780 |
112574 |
0 |
3 |
T4 |
151640 |
151420 |
0 |
3 |
T5 |
88449 |
88298 |
0 |
3 |
T6 |
3270 |
3050 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
39300 |
39094 |
0 |
3 |
T17 |
15557 |
15460 |
0 |
3 |
T18 |
26545 |
25863 |
0 |
3 |
T19 |
8391 |
8213 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
590418230 |
25710 |
0 |
0 |
T1 |
250862 |
141 |
0 |
0 |
T2 |
112780 |
0 |
0 |
0 |
T4 |
151640 |
0 |
0 |
0 |
T5 |
88449 |
0 |
0 |
0 |
T7 |
2346 |
43 |
0 |
0 |
T16 |
39300 |
43 |
0 |
0 |
T17 |
15557 |
7 |
0 |
0 |
T18 |
26545 |
62 |
0 |
0 |
T19 |
8391 |
0 |
0 |
0 |
T20 |
1625 |
0 |
0 |
0 |
T71 |
0 |
31 |
0 |
0 |
T82 |
0 |
44 |
0 |
0 |
T106 |
0 |
58 |
0 |
0 |
T107 |
0 |
47 |
0 |
0 |
T109 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157756518 |
0 |
2415 |
T1 |
654530 |
651829 |
0 |
3 |
T2 |
43469 |
43388 |
0 |
3 |
T4 |
94744 |
94638 |
0 |
3 |
T5 |
120918 |
120762 |
0 |
3 |
T6 |
817 |
760 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
2046 |
2033 |
0 |
3 |
T17 |
809 |
802 |
0 |
3 |
T18 |
6912 |
6728 |
0 |
3 |
T19 |
2184 |
2136 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
16013 |
0 |
0 |
T1 |
654530 |
80 |
0 |
0 |
T2 |
43469 |
0 |
0 |
0 |
T4 |
94744 |
0 |
0 |
0 |
T5 |
120918 |
0 |
0 |
0 |
T7 |
2346 |
41 |
0 |
0 |
T16 |
2046 |
48 |
0 |
0 |
T17 |
809 |
14 |
0 |
0 |
T18 |
6912 |
42 |
0 |
0 |
T19 |
2184 |
0 |
0 |
0 |
T20 |
1505 |
0 |
0 |
0 |
T71 |
0 |
8 |
0 |
0 |
T82 |
0 |
52 |
0 |
0 |
T106 |
0 |
33 |
0 |
0 |
T107 |
0 |
35 |
0 |
0 |
T109 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T1,T7,T16 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T7,T16 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157756518 |
0 |
2415 |
T1 |
654530 |
651829 |
0 |
3 |
T2 |
43469 |
43388 |
0 |
3 |
T4 |
94744 |
94638 |
0 |
3 |
T5 |
120918 |
120762 |
0 |
3 |
T6 |
817 |
760 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
2046 |
2033 |
0 |
3 |
T17 |
809 |
802 |
0 |
3 |
T18 |
6912 |
6728 |
0 |
3 |
T19 |
2184 |
2136 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
18465 |
0 |
0 |
T1 |
654530 |
113 |
0 |
0 |
T2 |
43469 |
0 |
0 |
0 |
T4 |
94744 |
0 |
0 |
0 |
T5 |
120918 |
0 |
0 |
0 |
T7 |
2346 |
44 |
0 |
0 |
T16 |
2046 |
45 |
0 |
0 |
T17 |
809 |
5 |
0 |
0 |
T18 |
6912 |
31 |
0 |
0 |
T19 |
2184 |
0 |
0 |
0 |
T20 |
1505 |
0 |
0 |
0 |
T71 |
0 |
13 |
0 |
0 |
T82 |
0 |
47 |
0 |
0 |
T106 |
0 |
28 |
0 |
0 |
T107 |
0 |
18 |
0 |
0 |
T109 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
623136957 |
0 |
0 |
T1 |
270923 |
270337 |
0 |
0 |
T2 |
117484 |
117372 |
0 |
0 |
T4 |
187964 |
187823 |
0 |
0 |
T5 |
116139 |
116084 |
0 |
0 |
T6 |
3407 |
3266 |
0 |
0 |
T7 |
2445 |
2362 |
0 |
0 |
T16 |
40939 |
40827 |
0 |
0 |
T17 |
16205 |
16151 |
0 |
0 |
T18 |
27652 |
27354 |
0 |
0 |
T19 |
8742 |
8630 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
623136957 |
0 |
0 |
T1 |
270923 |
270337 |
0 |
0 |
T2 |
117484 |
117372 |
0 |
0 |
T4 |
187964 |
187823 |
0 |
0 |
T5 |
116139 |
116084 |
0 |
0 |
T6 |
3407 |
3266 |
0 |
0 |
T7 |
2445 |
2362 |
0 |
0 |
T16 |
40939 |
40827 |
0 |
0 |
T17 |
16205 |
16151 |
0 |
0 |
T18 |
27652 |
27354 |
0 |
0 |
T19 |
8742 |
8630 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
590418230 |
588316702 |
0 |
0 |
T1 |
250862 |
250300 |
0 |
0 |
T2 |
112780 |
112673 |
0 |
0 |
T4 |
151640 |
151505 |
0 |
0 |
T5 |
88449 |
88397 |
0 |
0 |
T6 |
3270 |
3136 |
0 |
0 |
T7 |
2346 |
2266 |
0 |
0 |
T16 |
39300 |
39193 |
0 |
0 |
T17 |
15557 |
15504 |
0 |
0 |
T18 |
26545 |
26259 |
0 |
0 |
T19 |
8391 |
8284 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
590418230 |
588316702 |
0 |
0 |
T1 |
250862 |
250300 |
0 |
0 |
T2 |
112780 |
112673 |
0 |
0 |
T4 |
151640 |
151505 |
0 |
0 |
T5 |
88449 |
88397 |
0 |
0 |
T6 |
3270 |
3136 |
0 |
0 |
T7 |
2346 |
2266 |
0 |
0 |
T16 |
39300 |
39193 |
0 |
0 |
T17 |
15557 |
15504 |
0 |
0 |
T18 |
26545 |
26259 |
0 |
0 |
T19 |
8391 |
8284 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
296696049 |
296696049 |
0 |
0 |
T1 |
125306 |
125306 |
0 |
0 |
T2 |
56337 |
56337 |
0 |
0 |
T4 |
75753 |
75753 |
0 |
0 |
T5 |
44199 |
44199 |
0 |
0 |
T6 |
1568 |
1568 |
0 |
0 |
T7 |
1889 |
1889 |
0 |
0 |
T16 |
24630 |
24630 |
0 |
0 |
T17 |
8500 |
8500 |
0 |
0 |
T18 |
13907 |
13907 |
0 |
0 |
T19 |
4142 |
4142 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
296696049 |
296696049 |
0 |
0 |
T1 |
125306 |
125306 |
0 |
0 |
T2 |
56337 |
56337 |
0 |
0 |
T4 |
75753 |
75753 |
0 |
0 |
T5 |
44199 |
44199 |
0 |
0 |
T6 |
1568 |
1568 |
0 |
0 |
T7 |
1889 |
1889 |
0 |
0 |
T16 |
24630 |
24630 |
0 |
0 |
T17 |
8500 |
8500 |
0 |
0 |
T18 |
13907 |
13907 |
0 |
0 |
T19 |
4142 |
4142 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
148347463 |
148347463 |
0 |
0 |
T1 |
626530 |
626530 |
0 |
0 |
T2 |
28168 |
28168 |
0 |
0 |
T4 |
37876 |
37876 |
0 |
0 |
T5 |
22099 |
22099 |
0 |
0 |
T6 |
784 |
784 |
0 |
0 |
T7 |
944 |
944 |
0 |
0 |
T16 |
12315 |
12315 |
0 |
0 |
T17 |
4250 |
4250 |
0 |
0 |
T18 |
6953 |
6953 |
0 |
0 |
T19 |
2071 |
2071 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
148347463 |
148347463 |
0 |
0 |
T1 |
626530 |
626530 |
0 |
0 |
T2 |
28168 |
28168 |
0 |
0 |
T4 |
37876 |
37876 |
0 |
0 |
T5 |
22099 |
22099 |
0 |
0 |
T6 |
784 |
784 |
0 |
0 |
T7 |
944 |
944 |
0 |
0 |
T16 |
12315 |
12315 |
0 |
0 |
T17 |
4250 |
4250 |
0 |
0 |
T18 |
6953 |
6953 |
0 |
0 |
T19 |
2071 |
2071 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
300008036 |
298951914 |
0 |
0 |
T1 |
130527 |
130265 |
0 |
0 |
T2 |
56393 |
56339 |
0 |
0 |
T4 |
93104 |
93037 |
0 |
0 |
T5 |
49988 |
49962 |
0 |
0 |
T6 |
1635 |
1568 |
0 |
0 |
T7 |
1173 |
1134 |
0 |
0 |
T16 |
19651 |
19597 |
0 |
0 |
T17 |
7778 |
7752 |
0 |
0 |
T18 |
13273 |
13130 |
0 |
0 |
T19 |
4196 |
4142 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
300008036 |
298951914 |
0 |
0 |
T1 |
130527 |
130265 |
0 |
0 |
T2 |
56393 |
56339 |
0 |
0 |
T4 |
93104 |
93037 |
0 |
0 |
T5 |
49988 |
49962 |
0 |
0 |
T6 |
1635 |
1568 |
0 |
0 |
T7 |
1173 |
1134 |
0 |
0 |
T16 |
19651 |
19597 |
0 |
0 |
T17 |
7778 |
7752 |
0 |
0 |
T18 |
13273 |
13130 |
0 |
0 |
T19 |
4196 |
4142 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157756518 |
0 |
2415 |
T1 |
654530 |
651829 |
0 |
3 |
T2 |
43469 |
43388 |
0 |
3 |
T4 |
94744 |
94638 |
0 |
3 |
T5 |
120918 |
120762 |
0 |
3 |
T6 |
817 |
760 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
2046 |
2033 |
0 |
3 |
T17 |
809 |
802 |
0 |
3 |
T18 |
6912 |
6728 |
0 |
3 |
T19 |
2184 |
2136 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157756518 |
0 |
2415 |
T1 |
654530 |
651829 |
0 |
3 |
T2 |
43469 |
43388 |
0 |
3 |
T4 |
94744 |
94638 |
0 |
3 |
T5 |
120918 |
120762 |
0 |
3 |
T6 |
817 |
760 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
2046 |
2033 |
0 |
3 |
T17 |
809 |
802 |
0 |
3 |
T18 |
6912 |
6728 |
0 |
3 |
T19 |
2184 |
2136 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157756518 |
0 |
2415 |
T1 |
654530 |
651829 |
0 |
3 |
T2 |
43469 |
43388 |
0 |
3 |
T4 |
94744 |
94638 |
0 |
3 |
T5 |
120918 |
120762 |
0 |
3 |
T6 |
817 |
760 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
2046 |
2033 |
0 |
3 |
T17 |
809 |
802 |
0 |
3 |
T18 |
6912 |
6728 |
0 |
3 |
T19 |
2184 |
2136 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157756518 |
0 |
2415 |
T1 |
654530 |
651829 |
0 |
3 |
T2 |
43469 |
43388 |
0 |
3 |
T4 |
94744 |
94638 |
0 |
3 |
T5 |
120918 |
120762 |
0 |
3 |
T6 |
817 |
760 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
2046 |
2033 |
0 |
3 |
T17 |
809 |
802 |
0 |
3 |
T18 |
6912 |
6728 |
0 |
3 |
T19 |
2184 |
2136 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157756518 |
0 |
2415 |
T1 |
654530 |
651829 |
0 |
3 |
T2 |
43469 |
43388 |
0 |
3 |
T4 |
94744 |
94638 |
0 |
3 |
T5 |
120918 |
120762 |
0 |
3 |
T6 |
817 |
760 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
2046 |
2033 |
0 |
3 |
T17 |
809 |
802 |
0 |
3 |
T18 |
6912 |
6728 |
0 |
3 |
T19 |
2184 |
2136 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157756518 |
0 |
2415 |
T1 |
654530 |
651829 |
0 |
3 |
T2 |
43469 |
43388 |
0 |
3 |
T4 |
94744 |
94638 |
0 |
3 |
T5 |
120918 |
120762 |
0 |
3 |
T6 |
817 |
760 |
0 |
3 |
T7 |
2346 |
2222 |
0 |
3 |
T16 |
2046 |
2033 |
0 |
3 |
T17 |
809 |
802 |
0 |
3 |
T18 |
6912 |
6728 |
0 |
3 |
T19 |
2184 |
2136 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160110694 |
157763714 |
0 |
0 |
T1 |
654530 |
651847 |
0 |
0 |
T2 |
43469 |
43391 |
0 |
0 |
T4 |
94744 |
94641 |
0 |
0 |
T5 |
120918 |
120765 |
0 |
0 |
T6 |
817 |
763 |
0 |
0 |
T7 |
2346 |
2225 |
0 |
0 |
T16 |
2046 |
2036 |
0 |
0 |
T17 |
809 |
805 |
0 |
0 |
T18 |
6912 |
6740 |
0 |
0 |
T19 |
2184 |
2139 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620992909 |
0 |
2415 |
T1 |
270923 |
269803 |
0 |
3 |
T2 |
117484 |
117269 |
0 |
3 |
T4 |
187964 |
187735 |
0 |
3 |
T5 |
116139 |
115981 |
0 |
3 |
T6 |
3407 |
3178 |
0 |
3 |
T7 |
2445 |
2316 |
0 |
3 |
T16 |
40939 |
40724 |
0 |
3 |
T17 |
16205 |
16105 |
0 |
3 |
T18 |
27652 |
26941 |
0 |
3 |
T19 |
8742 |
8555 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
32045 |
0 |
0 |
T1 |
270923 |
297 |
0 |
0 |
T2 |
117484 |
1 |
0 |
0 |
T4 |
187964 |
1 |
0 |
0 |
T5 |
116139 |
1 |
0 |
0 |
T6 |
3407 |
2 |
0 |
0 |
T7 |
2445 |
15 |
0 |
0 |
T16 |
40939 |
15 |
0 |
0 |
T17 |
16205 |
3 |
0 |
0 |
T18 |
27652 |
99 |
0 |
0 |
T19 |
8742 |
34 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620992909 |
0 |
2415 |
T1 |
270923 |
269803 |
0 |
3 |
T2 |
117484 |
117269 |
0 |
3 |
T4 |
187964 |
187735 |
0 |
3 |
T5 |
116139 |
115981 |
0 |
3 |
T6 |
3407 |
3178 |
0 |
3 |
T7 |
2445 |
2316 |
0 |
3 |
T16 |
40939 |
40724 |
0 |
3 |
T17 |
16205 |
16105 |
0 |
3 |
T18 |
27652 |
26941 |
0 |
3 |
T19 |
8742 |
8555 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
32099 |
0 |
0 |
T1 |
270923 |
282 |
0 |
0 |
T2 |
117484 |
1 |
0 |
0 |
T4 |
187964 |
1 |
0 |
0 |
T5 |
116139 |
1 |
0 |
0 |
T6 |
3407 |
4 |
0 |
0 |
T7 |
2445 |
11 |
0 |
0 |
T16 |
40939 |
11 |
0 |
0 |
T17 |
16205 |
3 |
0 |
0 |
T18 |
27652 |
80 |
0 |
0 |
T19 |
8742 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620992909 |
0 |
2415 |
T1 |
270923 |
269803 |
0 |
3 |
T2 |
117484 |
117269 |
0 |
3 |
T4 |
187964 |
187735 |
0 |
3 |
T5 |
116139 |
115981 |
0 |
3 |
T6 |
3407 |
3178 |
0 |
3 |
T7 |
2445 |
2316 |
0 |
3 |
T16 |
40939 |
40724 |
0 |
3 |
T17 |
16205 |
16105 |
0 |
3 |
T18 |
27652 |
26941 |
0 |
3 |
T19 |
8742 |
8555 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
32472 |
0 |
0 |
T1 |
270923 |
297 |
0 |
0 |
T2 |
117484 |
1 |
0 |
0 |
T4 |
187964 |
1 |
0 |
0 |
T5 |
116139 |
1 |
0 |
0 |
T6 |
3407 |
6 |
0 |
0 |
T7 |
2445 |
11 |
0 |
0 |
T16 |
40939 |
17 |
0 |
0 |
T17 |
16205 |
5 |
0 |
0 |
T18 |
27652 |
91 |
0 |
0 |
T19 |
8742 |
34 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T1,T7 |
1 | Covered | T6,T1,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T1,T7 |
0 |
Covered |
T6,T1,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620992909 |
0 |
2415 |
T1 |
270923 |
269803 |
0 |
3 |
T2 |
117484 |
117269 |
0 |
3 |
T4 |
187964 |
187735 |
0 |
3 |
T5 |
116139 |
115981 |
0 |
3 |
T6 |
3407 |
3178 |
0 |
3 |
T7 |
2445 |
2316 |
0 |
3 |
T16 |
40939 |
40724 |
0 |
3 |
T17 |
16205 |
16105 |
0 |
3 |
T18 |
27652 |
26941 |
0 |
3 |
T19 |
8742 |
8555 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
32163 |
0 |
0 |
T1 |
270923 |
285 |
0 |
0 |
T2 |
117484 |
1 |
0 |
0 |
T4 |
187964 |
1 |
0 |
0 |
T5 |
116139 |
1 |
0 |
0 |
T6 |
3407 |
10 |
0 |
0 |
T7 |
2445 |
11 |
0 |
0 |
T16 |
40939 |
13 |
0 |
0 |
T17 |
16205 |
5 |
0 |
0 |
T18 |
27652 |
90 |
0 |
0 |
T19 |
8742 |
27 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
625335565 |
620999964 |
0 |
0 |
T1 |
270923 |
269805 |
0 |
0 |
T2 |
117484 |
117272 |
0 |
0 |
T4 |
187964 |
187738 |
0 |
0 |
T5 |
116139 |
115984 |
0 |
0 |
T6 |
3407 |
3181 |
0 |
0 |
T7 |
2445 |
2319 |
0 |
0 |
T16 |
40939 |
40727 |
0 |
0 |
T17 |
16205 |
16108 |
0 |
0 |
T18 |
27652 |
26953 |
0 |
0 |
T19 |
8742 |
8558 |
0 |
0 |