Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T1,T18,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	160110694	157639400	0	0
AllClkBypReqTrue_A	160110694	121984	0	0
IoClkBypReqFalse_A	160110694	157567913	0	2415
IoClkBypReqTrue_A	160110694	188811	0	0
LcClkBypAckFalse_A	160110694	157648938	0	0
LcClkBypAckTrue_A	160110694	112446	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	157639400	0	0
T1	654530	650879	0	0
T2	43469	43390	0	0
T4	94744	94640	0	0
T5	120918	120764	0	0
T6	817	762	0	0
T7	2346	1927	0	0
T16	2046	1723	0	0
T17	809	761	0	0
T18	6912	6583	0	0
T19	2184	2138	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	121984	0	0
T1	654530	962	0	0
T2	43469	0	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	297	0	0
T16	2046	312	0	0
T17	809	43	0	0
T18	6912	153	0	0
T19	2184	0	0	0
T20	1505	0	0	0
T71	0	56	0	0
T82	0	304	0	0
T106	0	87	0	0
T107	0	34	0	0
T108	0	11	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	157567913	0	2415
T1	654530	650674	0	3
T2	43469	43388	0	3
T4	94744	94638	0	3
T5	120918	120762	0	3
T6	817	760	0	3
T7	2346	1903	0	3
T16	2046	1651	0	3
T17	809	722	0	3
T18	6912	6341	0	3
T19	2184	2136	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	188811	0	0
T1	654530	1155	0	0
T2	43469	0	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	319	0	0
T16	2046	382	0	0
T17	809	80	0	0
T18	6912	387	0	0
T19	2184	0	0	0
T20	1505	0	0	0
T71	0	86	0	0
T82	0	354	0	0
T106	0	386	0	0
T107	0	321	0	0
T109	0	55	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	157648938	0	0
T1	654530	651197	0	0
T2	43469	43390	0	0
T4	94744	94640	0	0
T5	120918	120764	0	0
T6	817	762	0	0
T7	2346	2018	0	0
T16	2046	1808	0	0
T17	809	744	0	0
T18	6912	6429	0	0
T19	2184	2138	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	112446	0	0
T1	654530	644	0	0
T2	43469	0	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	206	0	0
T16	2046	227	0	0
T17	809	60	0	0
T18	6912	307	0	0
T19	2184	0	0	0
T20	1505	0	0	0
T71	0	48	0	0
T82	0	250	0	0
T106	0	262	0	0
T107	0	201	0	0
T109	0	45	0	0