Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	15934	0	0
TransStop_A	2147483647	8149	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15934	0	0
T1	1083692	151	0	0
T2	469940	0	0	0
T3	0	8	0	0
T4	751860	0	0	0
T5	464556	0	0	0
T7	9780	0	0	0
T16	163756	0	0	0
T17	64820	0	0	0
T18	110612	40	0	0
T19	34968	24	0	0
T20	6772	4	0	0
T93	0	26	0	0
T94	0	24	0	0
T110	0	39	0	0
T111	0	10	0	0
T112	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8149	0	0
T1	1083692	97	0	0
T2	469940	0	0	0
T3	0	8	0	0
T4	751860	0	0	0
T5	464556	0	0	0
T7	9780	0	0	0
T16	163756	0	0	0
T17	64820	0	0	0
T18	110612	23	0	0
T19	34968	18	0	0
T20	6772	4	0	0
T93	0	15	0	0
T94	0	10	0	0
T110	0	24	0	0
T111	0	6	0	0
T112	0	8	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	625336007	4049	0	0
TransStop_A	625336007	2047	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625336007	4049	0	0
T1	270923	36	0	0
T2	117485	0	0	0
T3	0	2	0	0
T4	187965	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27653	9	0	0
T19	8742	4	0	0
T20	1693	1	0	0
T93	0	10	0	0
T94	0	4	0	0
T110	0	8	0	0
T111	0	3	0	0
T112	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625336007	2047	0	0
T1	270923	25	0	0
T2	117485	0	0	0
T3	0	2	0	0
T4	187965	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27653	5	0	0
T19	8742	3	0	0
T20	1693	1	0	0
T93	0	6	0	0
T94	0	2	0	0
T110	0	7	0	0
T111	0	2	0	0
T112	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	625336007	3936	0	0
TransStop_A	625336007	2036	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625336007	3936	0	0
T1	270923	39	0	0
T2	117485	0	0	0
T3	0	2	0	0
T4	187965	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27653	11	0	0
T19	8742	7	0	0
T20	1693	1	0	0
T93	0	7	0	0
T94	0	8	0	0
T110	0	12	0	0
T111	0	3	0	0
T112	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625336007	2036	0	0
T1	270923	27	0	0
T2	117485	0	0	0
T3	0	2	0	0
T4	187965	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27653	7	0	0
T19	8742	5	0	0
T20	1693	1	0	0
T93	0	3	0	0
T94	0	4	0	0
T110	0	6	0	0
T111	0	2	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	625336007	3972	0	0
TransStop_A	625336007	2026	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625336007	3972	0	0
T1	270923	38	0	0
T2	117485	0	0	0
T3	0	2	0	0
T4	187965	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27653	8	0	0
T19	8742	7	0	0
T20	1693	1	0	0
T93	0	4	0	0
T94	0	6	0	0
T110	0	9	0	0
T111	0	1	0	0
T112	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625336007	2026	0	0
T1	270923	22	0	0
T2	117485	0	0	0
T3	0	2	0	0
T4	187965	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27653	4	0	0
T19	8742	6	0	0
T20	1693	1	0	0
T93	0	3	0	0
T94	0	1	0	0
T110	0	4	0	0
T111	0	1	0	0
T112	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	625336007	3977	0	0
TransStop_A	625336007	2040	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625336007	3977	0	0
T1	270923	38	0	0
T2	117485	0	0	0
T3	0	2	0	0
T4	187965	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27653	12	0	0
T19	8742	6	0	0
T20	1693	1	0	0
T93	0	5	0	0
T94	0	6	0	0
T110	0	10	0	0
T111	0	3	0	0
T112	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625336007	2040	0	0
T1	270923	23	0	0
T2	117485	0	0	0
T3	0	2	0	0
T4	187965	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27653	7	0	0
T19	8742	4	0	0
T20	1693	1	0	0
T93	0	3	0	0
T94	0	3	0	0
T110	0	7	0	0
T111	0	1	0	0
T112	0	2	0	0