Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT6,T1,T7
10CoveredT1,T7,T16 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T7,T16
11CoveredT1,T7,T16 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T7,T16
10CoveredT6,T1,T7
11CoveredT6,T1,T7
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 739202435 739200020 0 0
selKnown1 1771254690 1771252275 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 739202435 739200020 0 0
T1 876986 876985 0 0
T2 140842 140839 0 0
T4 189382 189379 0 0
T5 110497 110494 0 0
T6 3920 3917 0 0
T7 3966 3963 0 0
T16 56542 56539 0 0
T17 20502 20499 0 0
T18 33991 33988 0 0
T19 10355 10352 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1771254690 1771252275 0 0
T1 752586 752586 0 0
T2 338340 338337 0 0
T4 454920 454917 0 0
T5 265347 265344 0 0
T6 9810 9807 0 0
T7 7038 7035 0 0
T16 117900 117897 0 0
T17 46671 46668 0 0
T18 79635 79632 0 0
T19 25173 25170 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT6,T1,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T1,T7
11CoveredT6,T1,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 296696049 296695244 0 0
selKnown1 590418230 590417425 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 296696049 296695244 0 0
T1 125306 125306 0 0
T2 56337 56336 0 0
T4 75753 75752 0 0
T5 44199 44198 0 0
T6 1568 1567 0 0
T7 1889 1888 0 0
T16 24630 24629 0 0
T17 8500 8499 0 0
T18 13907 13906 0 0
T19 4142 4141 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 590418230 590417425 0 0
T1 250862 250862 0 0
T2 112780 112779 0 0
T4 151640 151639 0 0
T5 88449 88448 0 0
T6 3270 3269 0 0
T7 2346 2345 0 0
T16 39300 39299 0 0
T17 15557 15556 0 0
T18 26545 26544 0 0
T19 8391 8390 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT6,T1,T7
10CoveredT1,T7,T16 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T7,T16
11CoveredT1,T7,T16 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T7,T16
10CoveredT6,T1,T7
11CoveredT6,T1,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 294158923 294158118 0 0
selKnown1 590418230 590417425 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 294158923 294158118 0 0
T1 125150 125150 0 0
T2 56337 56336 0 0
T4 75753 75752 0 0
T5 44199 44198 0 0
T6 1568 1567 0 0
T7 1133 1132 0 0
T16 19597 19596 0 0
T17 7752 7751 0 0
T18 13131 13130 0 0
T19 4142 4141 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 590418230 590417425 0 0
T1 250862 250862 0 0
T2 112780 112779 0 0
T4 151640 151639 0 0
T5 88449 88448 0 0
T6 3270 3269 0 0
T7 2346 2345 0 0
T16 39300 39299 0 0
T17 15557 15556 0 0
T18 26545 26544 0 0
T19 8391 8390 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T1,T7
01CoveredT6,T1,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T1,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T1,T7
11CoveredT6,T1,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 148347463 148346658 0 0
selKnown1 590418230 590417425 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 148347463 148346658 0 0
T1 626530 626529 0 0
T2 28168 28167 0 0
T4 37876 37875 0 0
T5 22099 22098 0 0
T6 784 783 0 0
T7 944 943 0 0
T16 12315 12314 0 0
T17 4250 4249 0 0
T18 6953 6952 0 0
T19 2071 2070 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 590418230 590417425 0 0
T1 250862 250862 0 0
T2 112780 112779 0 0
T4 151640 151639 0 0
T5 88449 88448 0 0
T6 3270 3269 0 0
T7 2346 2345 0 0
T16 39300 39299 0 0
T17 15557 15556 0 0
T18 26545 26544 0 0
T19 8391 8390 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%