Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	160110694	17405442	0	55

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	17405442	0	55
T1	654530	171414	0	0
T2	43469	5512	0	1
T3	0	10064	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	0	0	0
T9	0	1666	0	1
T10	0	12490	0	1
T11	0	9467	0	0
T12	0	51912	0	1
T13	0	745798	0	0
T16	2046	0	0	0
T17	809	0	0	0
T18	6912	0	0	0
T19	2184	0	0	0
T20	1505	0	0	0
T21	0	686	0	1
T22	0	931	0	1
T23	0	0	0	1
T114	0	0	0	1
T115	0	0	0	1
T116	0	0	0	1