Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	161050006	5731647	0	0
clk_enables_rd_A	161050006	30234	0	0
clk_hints_rd_A	161050006	26478	0	0
extclk_ctrl_rd_A	161050006	36794	0	0
extclk_ctrl_regwen_rd_A	161050006	26515	0	0
jitter_enable_rd_A	161050006	39868	0	0
jitter_regwen_rd_A	161050006	28889	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161050006	5731647	0	0
T1	654530	21918	0	0
T2	43469	0	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	0	0	0
T13	0	138422	0	0
T14	0	39196	0	0
T15	0	79208	0	0
T16	2046	0	0	0
T17	809	0	0	0
T18	6912	0	0	0
T19	2184	0	0	0
T20	1505	0	0	0
T31	0	107291	0	0
T66	0	7849	0	0
T67	0	91745	0	0
T68	0	242886	0	0
T69	0	30979	0	0
T70	0	180381	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161050006	30234	0	0
T3	54271	2	0	0
T12	0	2	0	0
T14	0	1535	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	0	0	0
T47	0	6	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T109	848	0	0	0
T111	843	0	0	0
T131	0	3	0	0
T132	0	2	0	0
T133	0	2	0	0
T134	0	8	0	0
T135	0	1	0	0
T136	0	2724	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161050006	26478	0	0
T3	54271	13	0	0
T12	0	8	0	0
T14	0	1412	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	0	0	0
T47	0	9	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T109	848	0	0	0
T111	843	0	0	0
T131	0	3	0	0
T132	0	1	0	0
T133	0	7	0	0
T134	0	2	0	0
T136	0	2428	0	0
T137	0	9	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161050006	36794	0	0
T2	43469	0	0	0
T4	94744	0	0	0
T5	120918	0	0	0
T7	2346	38	0	0
T16	2046	45	0	0
T17	809	0	0	0
T18	6912	0	0	0
T19	2184	0	0	0
T20	1505	0	0	0
T26	0	130	0	0
T71	1739	0	0	0
T106	0	68	0	0
T138	0	10	0	0
T139	0	11	0	0
T140	0	27	0	0
T141	0	1	0	0
T142	0	59	0	0
T143	0	11	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161050006	26515	0	0
T10	64695	0	0	0
T14	0	1355	0	0
T26	31729	42	0	0
T36	1154	0	0	0
T72	0	25	0	0
T105	0	38	0	0
T144	0	79	0	0
T145	0	6	0	0
T146	0	36	0	0
T147	0	7	0	0
T148	0	14	0	0
T149	0	43	0	0
T150	947	0	0	0
T151	1548	0	0	0
T152	1726	0	0	0
T153	987	0	0	0
T154	2460	0	0	0
T155	2903	0	0	0
T156	1267	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161050006	39868	0	0
T3	54271	240	0	0
T12	0	249	0	0
T14	0	1857	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	0	0	0
T47	0	133	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T109	848	0	0	0
T111	843	0	0	0
T131	0	131	0	0
T132	0	97	0	0
T133	0	89	0	0
T134	0	108	0	0
T135	0	62	0	0
T136	0	3931	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161050006	28889	0	0
T14	137650	1501	0	0
T15	220266	0	0	0
T29	870	0	0	0
T73	28465	0	0	0
T83	1744	0	0	0
T105	10402	0	0	0
T136	0	2637	0	0
T157	0	1691	0	0
T158	0	772	0	0
T159	0	1264	0	0
T160	0	2653	0	0
T161	0	3402	0	0
T162	0	2186	0	0
T163	0	2876	0	0
T164	0	2073	0	0
T165	34783	0	0	0
T166	1601	0	0	0
T167	1108	0	0	0
T168	1239	0	0	0