Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T16,T18
11CoveredT1,T7,T16

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 590418673 4228 0 0
g_div2.Div2Whole_A 590418673 4909 0 0
g_div4.Div4Stepped_A 296696432 4158 0 0
g_div4.Div4Whole_A 296696432 4691 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 590418673 4228 0 0
T1 250862 26 0 0
T2 112781 0 0 0
T4 151641 0 0 0
T5 88450 0 0 0
T7 2347 10 0 0
T16 39300 8 0 0
T17 15557 2 0 0
T18 26546 13 0 0
T19 8391 0 0 0
T20 1625 0 0 0
T71 0 1 0 0
T82 0 11 0 0
T106 0 10 0 0
T107 0 7 0 0
T109 0 2 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 590418673 4909 0 0
T1 250862 27 0 0
T2 112781 0 0 0
T4 151641 0 0 0
T5 88450 0 0 0
T7 2347 10 0 0
T16 39300 8 0 0
T17 15557 2 0 0
T18 26546 13 0 0
T19 8391 0 0 0
T20 1625 0 0 0
T71 0 4 0 0
T82 0 11 0 0
T106 0 11 0 0
T107 0 9 0 0
T109 0 2 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 296696432 4158 0 0
T1 125306 26 0 0
T2 56337 0 0 0
T4 75753 0 0 0
T5 44199 0 0 0
T7 1890 9 0 0
T16 24630 8 0 0
T17 8501 2 0 0
T18 13907 13 0 0
T19 4143 0 0 0
T20 794 0 0 0
T71 0 1 0 0
T82 0 11 0 0
T106 0 10 0 0
T107 0 7 0 0
T109 0 2 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 296696432 4691 0 0
T1 125306 27 0 0
T2 56337 0 0 0
T4 75753 0 0 0
T5 44199 0 0 0
T7 1890 8 0 0
T16 24630 8 0 0
T17 8501 2 0 0
T18 13907 13 0 0
T19 4143 0 0 0
T20 794 0 0 0
T71 0 3 0 0
T82 0 11 0 0
T106 0 11 0 0
T107 0 9 0 0
T109 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T16,T18
11CoveredT1,T7,T16

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 590418673 4228 0 0
g_div2.Div2Whole_A 590418673 4909 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 590418673 4228 0 0
T1 250862 26 0 0
T2 112781 0 0 0
T4 151641 0 0 0
T5 88450 0 0 0
T7 2347 10 0 0
T16 39300 8 0 0
T17 15557 2 0 0
T18 26546 13 0 0
T19 8391 0 0 0
T20 1625 0 0 0
T71 0 1 0 0
T82 0 11 0 0
T106 0 10 0 0
T107 0 7 0 0
T109 0 2 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 590418673 4909 0 0
T1 250862 27 0 0
T2 112781 0 0 0
T4 151641 0 0 0
T5 88450 0 0 0
T7 2347 10 0 0
T16 39300 8 0 0
T17 15557 2 0 0
T18 26546 13 0 0
T19 8391 0 0 0
T20 1625 0 0 0
T71 0 4 0 0
T82 0 11 0 0
T106 0 11 0 0
T107 0 9 0 0
T109 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T1,T7
10CoveredT1,T16,T18
11CoveredT1,T7,T16

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 296696432 4158 0 0
g_div4.Div4Whole_A 296696432 4691 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 296696432 4158 0 0
T1 125306 26 0 0
T2 56337 0 0 0
T4 75753 0 0 0
T5 44199 0 0 0
T7 1890 9 0 0
T16 24630 8 0 0
T17 8501 2 0 0
T18 13907 13 0 0
T19 4143 0 0 0
T20 794 0 0 0
T71 0 1 0 0
T82 0 11 0 0
T106 0 10 0 0
T107 0 7 0 0
T109 0 2 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 296696432 4691 0 0
T1 125306 27 0 0
T2 56337 0 0 0
T4 75753 0 0 0
T5 44199 0 0 0
T7 1890 8 0 0
T16 24630 8 0 0
T17 8501 2 0 0
T18 13907 13 0 0
T19 4143 0 0 0
T20 794 0 0 0
T71 0 3 0 0
T82 0 11 0 0
T106 0 11 0 0
T107 0 9 0 0
T109 0 2 0 0

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