SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T1,T7 |
1 | 0 | Covered | T1,T16,T18 |
1 | 1 | Covered | T1,T7,T16 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 590418673 | 4228 | 0 | 0 |
g_div2.Div2Whole_A | 590418673 | 4909 | 0 | 0 |
g_div4.Div4Stepped_A | 296696432 | 4158 | 0 | 0 |
g_div4.Div4Whole_A | 296696432 | 4691 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 590418673 | 4228 | 0 | 0 |
T1 | 250862 | 26 | 0 | 0 |
T2 | 112781 | 0 | 0 | 0 |
T4 | 151641 | 0 | 0 | 0 |
T5 | 88450 | 0 | 0 | 0 |
T7 | 2347 | 10 | 0 | 0 |
T16 | 39300 | 8 | 0 | 0 |
T17 | 15557 | 2 | 0 | 0 |
T18 | 26546 | 13 | 0 | 0 |
T19 | 8391 | 0 | 0 | 0 |
T20 | 1625 | 0 | 0 | 0 |
T71 | 0 | 1 | 0 | 0 |
T82 | 0 | 11 | 0 | 0 |
T106 | 0 | 10 | 0 | 0 |
T107 | 0 | 7 | 0 | 0 |
T109 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 590418673 | 4909 | 0 | 0 |
T1 | 250862 | 27 | 0 | 0 |
T2 | 112781 | 0 | 0 | 0 |
T4 | 151641 | 0 | 0 | 0 |
T5 | 88450 | 0 | 0 | 0 |
T7 | 2347 | 10 | 0 | 0 |
T16 | 39300 | 8 | 0 | 0 |
T17 | 15557 | 2 | 0 | 0 |
T18 | 26546 | 13 | 0 | 0 |
T19 | 8391 | 0 | 0 | 0 |
T20 | 1625 | 0 | 0 | 0 |
T71 | 0 | 4 | 0 | 0 |
T82 | 0 | 11 | 0 | 0 |
T106 | 0 | 11 | 0 | 0 |
T107 | 0 | 9 | 0 | 0 |
T109 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 296696432 | 4158 | 0 | 0 |
T1 | 125306 | 26 | 0 | 0 |
T2 | 56337 | 0 | 0 | 0 |
T4 | 75753 | 0 | 0 | 0 |
T5 | 44199 | 0 | 0 | 0 |
T7 | 1890 | 9 | 0 | 0 |
T16 | 24630 | 8 | 0 | 0 |
T17 | 8501 | 2 | 0 | 0 |
T18 | 13907 | 13 | 0 | 0 |
T19 | 4143 | 0 | 0 | 0 |
T20 | 794 | 0 | 0 | 0 |
T71 | 0 | 1 | 0 | 0 |
T82 | 0 | 11 | 0 | 0 |
T106 | 0 | 10 | 0 | 0 |
T107 | 0 | 7 | 0 | 0 |
T109 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 296696432 | 4691 | 0 | 0 |
T1 | 125306 | 27 | 0 | 0 |
T2 | 56337 | 0 | 0 | 0 |
T4 | 75753 | 0 | 0 | 0 |
T5 | 44199 | 0 | 0 | 0 |
T7 | 1890 | 8 | 0 | 0 |
T16 | 24630 | 8 | 0 | 0 |
T17 | 8501 | 2 | 0 | 0 |
T18 | 13907 | 13 | 0 | 0 |
T19 | 4143 | 0 | 0 | 0 |
T20 | 794 | 0 | 0 | 0 |
T71 | 0 | 3 | 0 | 0 |
T82 | 0 | 11 | 0 | 0 |
T106 | 0 | 11 | 0 | 0 |
T107 | 0 | 9 | 0 | 0 |
T109 | 0 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T1,T7 |
1 | 0 | Covered | T1,T16,T18 |
1 | 1 | Covered | T1,T7,T16 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 590418673 | 4228 | 0 | 0 |
g_div2.Div2Whole_A | 590418673 | 4909 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 590418673 | 4228 | 0 | 0 |
T1 | 250862 | 26 | 0 | 0 |
T2 | 112781 | 0 | 0 | 0 |
T4 | 151641 | 0 | 0 | 0 |
T5 | 88450 | 0 | 0 | 0 |
T7 | 2347 | 10 | 0 | 0 |
T16 | 39300 | 8 | 0 | 0 |
T17 | 15557 | 2 | 0 | 0 |
T18 | 26546 | 13 | 0 | 0 |
T19 | 8391 | 0 | 0 | 0 |
T20 | 1625 | 0 | 0 | 0 |
T71 | 0 | 1 | 0 | 0 |
T82 | 0 | 11 | 0 | 0 |
T106 | 0 | 10 | 0 | 0 |
T107 | 0 | 7 | 0 | 0 |
T109 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 590418673 | 4909 | 0 | 0 |
T1 | 250862 | 27 | 0 | 0 |
T2 | 112781 | 0 | 0 | 0 |
T4 | 151641 | 0 | 0 | 0 |
T5 | 88450 | 0 | 0 | 0 |
T7 | 2347 | 10 | 0 | 0 |
T16 | 39300 | 8 | 0 | 0 |
T17 | 15557 | 2 | 0 | 0 |
T18 | 26546 | 13 | 0 | 0 |
T19 | 8391 | 0 | 0 | 0 |
T20 | 1625 | 0 | 0 | 0 |
T71 | 0 | 4 | 0 | 0 |
T82 | 0 | 11 | 0 | 0 |
T106 | 0 | 11 | 0 | 0 |
T107 | 0 | 9 | 0 | 0 |
T109 | 0 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T1,T7 |
1 | 0 | Covered | T1,T16,T18 |
1 | 1 | Covered | T1,T7,T16 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 296696432 | 4158 | 0 | 0 |
g_div4.Div4Whole_A | 296696432 | 4691 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 296696432 | 4158 | 0 | 0 |
T1 | 125306 | 26 | 0 | 0 |
T2 | 56337 | 0 | 0 | 0 |
T4 | 75753 | 0 | 0 | 0 |
T5 | 44199 | 0 | 0 | 0 |
T7 | 1890 | 9 | 0 | 0 |
T16 | 24630 | 8 | 0 | 0 |
T17 | 8501 | 2 | 0 | 0 |
T18 | 13907 | 13 | 0 | 0 |
T19 | 4143 | 0 | 0 | 0 |
T20 | 794 | 0 | 0 | 0 |
T71 | 0 | 1 | 0 | 0 |
T82 | 0 | 11 | 0 | 0 |
T106 | 0 | 10 | 0 | 0 |
T107 | 0 | 7 | 0 | 0 |
T109 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 296696432 | 4691 | 0 | 0 |
T1 | 125306 | 27 | 0 | 0 |
T2 | 56337 | 0 | 0 | 0 |
T4 | 75753 | 0 | 0 | 0 |
T5 | 44199 | 0 | 0 | 0 |
T7 | 1890 | 8 | 0 | 0 |
T16 | 24630 | 8 | 0 | 0 |
T17 | 8501 | 2 | 0 | 0 |
T18 | 13907 | 13 | 0 | 0 |
T19 | 4143 | 0 | 0 | 0 |
T20 | 794 | 0 | 0 | 0 |
T71 | 0 | 3 | 0 | 0 |
T82 | 0 | 11 | 0 | 0 |
T106 | 0 | 11 | 0 | 0 |
T107 | 0 | 9 | 0 | 0 |
T109 | 0 | 2 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |