Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	480332082	465	0	0
StatusRise_A	480332082	465	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480332082	465	0	0
T21	23094	0	0	0
T24	71901	0	0	0
T34	4671	9	0	0
T35	0	13	0	0
T36	0	14	0	0
T82	5430	0	0	0
T93	5499	0	0	0
T94	4848	0	0	0
T106	6966	0	0	0
T107	7638	0	0	0
T108	6321	0	0	0
T169	0	8	0	0
T170	0	15	0	0
T171	0	12	0	0
T172	0	10	0	0
T173	0	8	0	0
T174	0	6	0	0
T175	0	12	0	0
T176	5769	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480332082	465	0	0
T21	23094	0	0	0
T24	71901	0	0	0
T34	4671	9	0	0
T35	0	13	0	0
T36	0	14	0	0
T82	5430	0	0	0
T93	5499	0	0	0
T94	4848	0	0	0
T106	6966	0	0	0
T107	7638	0	0	0
T108	6321	0	0	0
T169	0	8	0	0
T170	0	15	0	0
T171	0	12	0	0
T172	0	10	0	0
T173	0	8	0	0
T174	0	6	0	0
T175	0	12	0	0
T176	5769	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	160110694	139	0	0
StatusRise_A	160110694	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	139	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T94	1616	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T108	2107	0	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	1923	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	139	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T94	1616	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T108	2107	0	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	1923	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	160110694	160	0	0
StatusRise_A	160110694	160	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	160	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T94	1616	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T108	2107	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	1923	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	160	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T94	1616	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T108	2107	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	1923	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	160110694	166	0	0
StatusRise_A	160110694	166	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	166	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	4	0	0
T35	0	7	0	0
T36	0	6	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T94	1616	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T108	2107	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0
T172	0	4	0	0
T173	0	3	0	0
T174	0	3	0	0
T175	0	2	0	0
T176	1923	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160110694	166	0	0
T21	7698	0	0	0
T24	23967	0	0	0
T34	1557	4	0	0
T35	0	7	0	0
T36	0	6	0	0
T82	1810	0	0	0
T93	1833	0	0	0
T94	1616	0	0	0
T106	2322	0	0	0
T107	2546	0	0	0
T108	2107	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0
T172	0	4	0	0
T173	0	3	0	0
T174	0	3	0	0
T175	0	2	0	0
T176	1923	0	0	0