Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48575	0	0
CgEnOn_A	2147483647	39248	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48575	0	0
T1	1273621	239	0	0
T2	314769	3	0	0
T4	453233	3	0	0
T5	270886	3	0	0
T6	5622	18	0	0
T7	7624	3	0	0
T16	117184	3	0	0
T17	44512	3	0	0
T18	75057	98	0	0
T19	23346	7	0	0
T20	1692	1	0	0
T21	72155	0	0	0
T24	189634	0	0	0
T34	3155	21	0	0
T35	0	20	0	0
T36	0	25	0	0
T82	73970	0	0	0
T93	10000	0	0	0
T94	13867	0	0	0
T106	22262	0	0	0
T107	5829	0	0	0
T108	21989	0	0	0
T169	0	10	0	0
T170	0	25	0	0
T171	0	25	0	0
T172	0	15	0	0
T173	0	15	0	0
T174	0	5	0	0
T175	0	30	0	0
T176	8800	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39248	0	0
T1	1273621	221	0	0
T2	314769	0	0	0
T3	0	8	0	0
T4	453233	0	0	0
T5	270886	0	0	0
T6	5622	15	0	0
T7	7624	0	0	0
T16	117184	0	0	0
T17	44512	0	0	0
T18	75057	86	0	0
T19	23346	4	0	0
T20	1692	4	0	0
T21	72155	0	0	0
T24	189634	0	0	0
T34	3155	33	0	0
T35	0	32	0	0
T36	0	25	0	0
T82	73970	0	0	0
T93	10000	0	0	0
T94	13867	0	0	0
T106	22262	0	0	0
T107	5829	0	0	0
T108	21989	0	0	0
T110	0	8	0	0
T111	0	3	0	0
T113	0	3	0	0
T131	0	3	0	0
T169	0	10	0	0
T170	0	25	0	0
T171	0	25	0	0
T172	0	15	0	0
T173	0	15	0	0
T174	0	5	0	0
T175	0	30	0	0
T176	8800	0	0	0
T177	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	296696049	161	0	0
CgEnOn_A	296696049	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296696049	161	0	0
T21	16011	0	0	0
T24	42114	0	0	0
T34	693	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	17997	0	0	0
T93	2195	0	0	0
T94	3064	0	0	0
T106	5190	0	0	0
T107	1315	0	0	0
T108	5118	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	2015	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296696049	161	0	0
T21	16011	0	0	0
T24	42114	0	0	0
T34	693	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	17997	0	0	0
T93	2195	0	0	0
T94	3064	0	0	0
T106	5190	0	0	0
T107	1315	0	0	0
T108	5118	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	2015	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	148347463	161	0	0
CgEnOn_A	148347463	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347463	161	0	0
T21	8005	0	0	0
T24	21057	0	0	0
T34	346	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	8997	0	0	0
T93	1098	0	0	0
T94	1532	0	0	0
T106	2594	0	0	0
T107	656	0	0	0
T108	2557	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	1006	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347463	161	0	0
T21	8005	0	0	0
T24	21057	0	0	0
T34	346	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	8997	0	0	0
T93	1098	0	0	0
T94	1532	0	0	0
T106	2594	0	0	0
T107	656	0	0	0
T108	2557	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	1006	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	148347463	161	0	0
CgEnOn_A	148347463	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347463	161	0	0
T21	8005	0	0	0
T24	21057	0	0	0
T34	346	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	8997	0	0	0
T93	1098	0	0	0
T94	1532	0	0	0
T106	2594	0	0	0
T107	656	0	0	0
T108	2557	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	1006	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347463	161	0	0
T21	8005	0	0	0
T24	21057	0	0	0
T34	346	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	8997	0	0	0
T93	1098	0	0	0
T94	1532	0	0	0
T106	2594	0	0	0
T107	656	0	0	0
T108	2557	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	1006	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	148347463	161	0	0
CgEnOn_A	148347463	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347463	161	0	0
T21	8005	0	0	0
T24	21057	0	0	0
T34	346	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	8997	0	0	0
T93	1098	0	0	0
T94	1532	0	0	0
T106	2594	0	0	0
T107	656	0	0	0
T108	2557	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	1006	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347463	161	0	0
T21	8005	0	0	0
T24	21057	0	0	0
T34	346	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	8997	0	0	0
T93	1098	0	0	0
T94	1532	0	0	0
T106	2594	0	0	0
T107	656	0	0	0
T108	2557	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	1006	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	590418230	161	0	0
CgEnOn_A	590418230	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590418230	161	0	0
T21	32129	0	0	0
T24	84349	0	0	0
T34	1424	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	28982	0	0	0
T93	4511	0	0	0
T94	6207	0	0	0
T106	9290	0	0	0
T107	2546	0	0	0
T108	9200	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	3767	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590418230	160	0	0
T21	32129	0	0	0
T24	84349	0	0	0
T34	1424	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T82	28982	0	0	0
T93	4511	0	0	0
T94	6207	0	0	0
T106	9290	0	0	0
T107	2546	0	0	0
T108	9200	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	6	0	0
T176	3767	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	625335565	140	0	0
CgEnOn_A	625335565	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	140	0	0
T21	33469	0	0	0
T24	87867	0	0	0
T34	1468	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T82	30190	0	0	0
T93	4698	0	0	0
T94	6466	0	0	0
T106	9678	0	0	0
T107	2653	0	0	0
T108	9583	0	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	3925	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	139	0	0
T21	33469	0	0	0
T24	87867	0	0	0
T34	1468	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T82	30190	0	0	0
T93	4698	0	0	0
T94	6466	0	0	0
T106	9678	0	0	0
T107	2653	0	0	0
T108	9583	0	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	3925	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	625335565	140	0	0
CgEnOn_A	625335565	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	140	0	0
T21	33469	0	0	0
T24	87867	0	0	0
T34	1468	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T82	30190	0	0	0
T93	4698	0	0	0
T94	6466	0	0	0
T106	9678	0	0	0
T107	2653	0	0	0
T108	9583	0	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	3925	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	139	0	0
T21	33469	0	0	0
T24	87867	0	0	0
T34	1468	1	0	0
T35	0	2	0	0
T36	0	3	0	0
T82	30190	0	0	0
T93	4698	0	0	0
T94	6466	0	0	0
T106	9678	0	0	0
T107	2653	0	0	0
T108	9583	0	0	0
T169	0	4	0	0
T170	0	5	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	3925	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Unreachable
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	300008036	168	0	0
CgEnOn_A	300008036	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300008036	168	0	0
T1	130527	1	0	0
T2	56393	0	0	0
T4	93104	0	0	0
T5	49988	0	0	0
T7	1173	0	0	0
T16	19651	0	0	0
T17	7778	0	0	0
T18	13273	0	0	0
T19	4196	0	0	0
T20	812	0	0	0
T34	0	4	0	0
T35	0	7	0	0
T36	0	6	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0
T172	0	4	0	0
T173	0	3	0	0
T174	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300008036	166	0	0
T21	16065	0	0	0
T24	47937	0	0	0
T34	664	4	0	0
T35	0	7	0	0
T36	0	6	0	0
T82	14492	0	0	0
T93	2255	0	0	0
T94	3103	0	0	0
T106	4645	0	0	0
T107	1274	0	0	0
T108	4599	0	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0
T172	0	4	0	0
T173	0	3	0	0
T174	0	3	0	0
T175	0	2	0	0
T176	1884	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	148347463	7672	0	0
CgEnOn_A	148347463	5343	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347463	7672	0	0
T1	626530	67	0	0
T2	28168	1	0	0
T4	37876	1	0	0
T5	22099	1	0	0
T6	784	5	0	0
T7	944	1	0	0
T16	12315	1	0	0
T17	4250	1	0	0
T18	6953	31	0	0
T19	2071	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148347463	5343	0	0
T1	626530	61	0	0
T2	28168	0	0	0
T3	0	2	0	0
T4	37876	0	0	0
T5	22099	0	0	0
T6	784	4	0	0
T7	944	0	0	0
T16	12315	0	0	0
T17	4250	0	0	0
T18	6953	27	0	0
T19	2071	0	0	0
T20	0	1	0	0
T34	0	4	0	0
T35	0	4	0	0
T113	0	1	0	0
T131	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	296696049	7721	0	0
CgEnOn_A	296696049	5392	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296696049	7721	0	0
T1	125306	68	0	0
T2	56337	1	0	0
T4	75753	1	0	0
T5	44199	1	0	0
T6	1568	6	0	0
T7	1889	1	0	0
T16	24630	1	0	0
T17	8500	1	0	0
T18	13907	28	0	0
T19	4142	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	296696049	5392	0	0
T1	125306	62	0	0
T2	56337	0	0	0
T3	0	2	0	0
T4	75753	0	0	0
T5	44199	0	0	0
T6	1568	5	0	0
T7	1889	0	0	0
T16	24630	0	0	0
T17	8500	0	0	0
T18	13907	24	0	0
T19	4142	0	0	0
T20	0	1	0	0
T34	0	4	0	0
T35	0	4	0	0
T113	0	1	0	0
T131	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	590418230	7715	0	0
CgEnOn_A	590418230	5385	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590418230	7715	0	0
T1	250862	68	0	0
T2	112780	1	0	0
T4	151640	1	0	0
T5	88449	1	0	0
T6	3270	7	0	0
T7	2346	1	0	0
T16	39300	1	0	0
T17	15557	1	0	0
T18	26545	30	0	0
T19	8391	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590418230	5385	0	0
T1	250862	62	0	0
T2	112780	0	0	0
T3	0	2	0	0
T4	151640	0	0	0
T5	88449	0	0	0
T6	3270	6	0	0
T7	2346	0	0	0
T16	39300	0	0	0
T17	15557	0	0	0
T18	26545	26	0	0
T19	8391	0	0	0
T20	0	1	0	0
T34	0	4	0	0
T35	0	4	0	0
T113	0	1	0	0
T131	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T6,T1,T7
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	300008036	7720	0	0
CgEnOn_A	300008036	5390	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300008036	7720	0	0
T1	130527	70	0	0
T2	56393	1	0	0
T4	93104	1	0	0
T5	49988	1	0	0
T6	1635	6	0	0
T7	1173	1	0	0
T16	19651	1	0	0
T17	7778	1	0	0
T18	13273	32	0	0
T19	4196	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300008036	5390	0	0
T1	130527	64	0	0
T2	56393	0	0	0
T3	0	2	0	0
T4	93104	0	0	0
T5	49988	0	0	0
T6	1635	5	0	0
T7	1173	0	0	0
T16	19651	0	0	0
T17	7778	0	0	0
T18	13273	28	0	0
T19	4196	0	0	0
T20	0	1	0	0
T34	0	4	0	0
T35	0	7	0	0
T113	0	1	0	0
T131	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Covered	T1,T18,T19
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	625335565	4189	0	0
CgEnOn_A	625335565	4188	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	4189	0	0
T1	270923	36	0	0
T2	117484	0	0	0
T3	0	2	0	0
T4	187964	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27652	9	0	0
T19	8742	4	0	0
T20	1692	1	0	0
T34	0	1	0	0
T93	0	10	0	0
T94	0	4	0	0
T110	0	8	0	0
T111	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	4188	0	0
T1	270923	36	0	0
T2	117484	0	0	0
T3	0	2	0	0
T4	187964	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27652	9	0	0
T19	8742	4	0	0
T20	1692	1	0	0
T34	0	1	0	0
T93	0	10	0	0
T94	0	4	0	0
T110	0	8	0	0
T111	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Covered	T1,T18,T19
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	625335565	4076	0	0
CgEnOn_A	625335565	4075	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	4076	0	0
T1	270923	39	0	0
T2	117484	0	0	0
T3	0	2	0	0
T4	187964	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27652	11	0	0
T19	8742	7	0	0
T20	1692	1	0	0
T34	0	1	0	0
T93	0	7	0	0
T94	0	8	0	0
T110	0	12	0	0
T111	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	4075	0	0
T1	270923	39	0	0
T2	117484	0	0	0
T3	0	2	0	0
T4	187964	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27652	11	0	0
T19	8742	7	0	0
T20	1692	1	0	0
T34	0	1	0	0
T93	0	7	0	0
T94	0	8	0	0
T110	0	12	0	0
T111	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Covered	T1,T18,T19
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	625335565	4112	0	0
CgEnOn_A	625335565	4111	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	4112	0	0
T1	270923	38	0	0
T2	117484	0	0	0
T3	0	2	0	0
T4	187964	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27652	8	0	0
T19	8742	7	0	0
T20	1692	1	0	0
T34	0	1	0	0
T93	0	4	0	0
T94	0	6	0	0
T110	0	9	0	0
T111	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	4111	0	0
T1	270923	38	0	0
T2	117484	0	0	0
T3	0	2	0	0
T4	187964	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27652	8	0	0
T19	8742	7	0	0
T20	1692	1	0	0
T34	0	1	0	0
T93	0	4	0	0
T94	0	6	0	0
T110	0	9	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T3
1	0	Covered	T1,T18,T19
1	1	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	625335565	4117	0	0
CgEnOn_A	625335565	4116	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	4117	0	0
T1	270923	38	0	0
T2	117484	0	0	0
T3	0	2	0	0
T4	187964	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27652	12	0	0
T19	8742	6	0	0
T20	1692	1	0	0
T34	0	1	0	0
T93	0	5	0	0
T94	0	6	0	0
T110	0	10	0	0
T111	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	625335565	4116	0	0
T1	270923	38	0	0
T2	117484	0	0	0
T3	0	2	0	0
T4	187964	0	0	0
T5	116139	0	0	0
T7	2445	0	0	0
T16	40939	0	0	0
T17	16205	0	0	0
T18	27652	12	0	0
T19	8742	6	0	0
T20	1692	1	0	0
T34	0	1	0	0
T93	0	5	0	0
T94	0	6	0	0
T110	0	10	0	0
T111	0	3	0	0