Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	633308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3568665

1

T7

24

T5

223

T26

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1031016	1			T7	25		T5	63		T26	6
values[0x0]	1458964	1			T7	16		T5	229		T26	9
values[0x1]	1711993	1			T7	15		T5	223		T26	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	351891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3850082

1

T7

27

T5

292

T26

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16378	1			T5	2		T2	203		T12	298
valid_sources[0x01]	16548	1			T5	5		T21	5		T2	178
valid_sources[0x02]	16485	1			T32	2		T21	1		T2	188
valid_sources[0x03]	17344	1			T5	3		T31	2		T32	2
valid_sources[0x04]	16525	1			T5	2		T32	1		T20	5
valid_sources[0x05]	15889	1			T5	1		T20	3		T21	3
valid_sources[0x06]	17504	1			T5	5		T31	1		T21	1
valid_sources[0x07]	13830	1			T5	9		T32	1		T2	227
valid_sources[0x08]	17064	1			T5	4		T21	2		T2	203
valid_sources[0x09]	15820	1			T7	4		T5	2		T21	1
valid_sources[0x0a]	14690	1			T7	3		T5	6		T21	5
valid_sources[0x0b]	15990	1			T28	2		T21	1		T2	202
valid_sources[0x0c]	16897	1			T5	2		T31	1		T2	201
valid_sources[0x0d]	16889	1			T5	7		T21	1		T2	176
valid_sources[0x0e]	15767	1			T5	2		T2	203		T4	1
valid_sources[0x0f]	17343	1			T5	1		T2	205		T4	2
valid_sources[0x10]	16957	1			T5	1		T21	2		T2	196
valid_sources[0x11]	15335	1			T5	1		T29	2		T21	1
valid_sources[0x12]	19306	1			T7	2		T5	2		T21	1
valid_sources[0x13]	15648	1			T20	1		T21	5		T2	203
valid_sources[0x14]	17609	1			T7	2		T21	1		T2	197
valid_sources[0x15]	15798	1			T5	1		T31	1		T2	196
valid_sources[0x16]	16348	1			T5	2		T32	1		T2	184
valid_sources[0x17]	15926	1			T5	1		T28	2		T29	1
valid_sources[0x18]	16406	1			T7	2		T5	2		T21	4
valid_sources[0x19]	15588	1			T7	3		T5	1		T32	1
valid_sources[0x1a]	16385	1			T7	3		T31	1		T20	3
valid_sources[0x1b]	15666	1			T32	1		T21	2		T2	176
valid_sources[0x1c]	16917	1			T5	1		T21	1		T2	169
valid_sources[0x1d]	17605	1			T28	1		T2	183		T4	4
valid_sources[0x1e]	14541	1			T5	2		T32	1		T21	1
valid_sources[0x1f]	15770	1			T5	5		T2	206		T23	1
valid_sources[0x20]	15810	1			T5	1		T31	2		T32	1
valid_sources[0x21]	17176	1			T5	12		T21	2		T2	181
valid_sources[0x22]	15836	1			T20	2		T21	2		T2	194
valid_sources[0x23]	17688	1			T5	1		T31	1		T32	1
valid_sources[0x24]	16390	1			T5	1		T21	1		T2	184
valid_sources[0x25]	15218	1			T5	1		T21	1		T2	196
valid_sources[0x26]	16031	1			T5	1		T21	2		T2	177
valid_sources[0x27]	17625	1			T5	4		T21	3		T2	231
valid_sources[0x28]	15368	1			T5	1		T2	186		T4	3
valid_sources[0x29]	16688	1			T5	2		T32	2		T21	1
valid_sources[0x2a]	16820	1			T21	2		T2	186		T25	4
valid_sources[0x2b]	17880	1			T5	2		T2	198		T4	3
valid_sources[0x2c]	15672	1			T5	4		T21	2		T2	213
valid_sources[0x2d]	15222	1			T2	189		T4	3		T25	7
valid_sources[0x2e]	16216	1			T5	1		T21	3		T2	186
valid_sources[0x2f]	16338	1			T5	1		T31	1		T2	177
valid_sources[0x30]	15435	1			T5	5		T21	1		T2	207
valid_sources[0x31]	15503	1			T5	4		T21	2		T2	205
valid_sources[0x32]	14936	1			T31	1		T2	181		T4	4
valid_sources[0x33]	15996	1			T5	4		T28	1		T32	1
valid_sources[0x34]	16900	1			T5	1		T2	204		T4	6
valid_sources[0x35]	15778	1			T5	1		T28	1		T30	1
valid_sources[0x36]	15990	1			T21	4		T2	216		T4	2
valid_sources[0x37]	17463	1			T21	3		T2	190		T4	1
valid_sources[0x38]	16020	1			T7	1		T5	2		T21	1
valid_sources[0x39]	16702	1			T5	2		T32	1		T21	1
valid_sources[0x3a]	16715	1			T5	2		T30	1		T2	203
valid_sources[0x3b]	15159	1			T21	5		T2	176		T4	3
valid_sources[0x3c]	15822	1			T7	1		T5	2		T28	2
valid_sources[0x3d]	15864	1			T28	2		T31	1		T32	1
valid_sources[0x3e]	16877	1			T5	3		T2	200		T4	6
valid_sources[0x3f]	16166	1			T31	2		T2	214		T4	4
valid_sources[0x40]	17045	1			T5	3		T28	1		T32	1
valid_sources[0x41]	17908	1			T5	2		T30	1		T2	211
valid_sources[0x42]	15824	1			T5	3		T28	2		T29	1
valid_sources[0x43]	18480	1			T2	196		T23	2		T4	5
valid_sources[0x44]	16045	1			T5	4		T21	2		T2	198
valid_sources[0x45]	15210	1			T7	4		T5	2		T28	1
valid_sources[0x46]	15892	1			T5	2		T32	1		T2	239
valid_sources[0x47]	15837	1			T5	2		T2	176		T4	1
valid_sources[0x48]	18738	1			T21	2		T2	193		T25	4
valid_sources[0x49]	15996	1			T5	3		T2	188		T23	1
valid_sources[0x4a]	18335	1			T2	212		T4	2		T25	1
valid_sources[0x4b]	16686	1			T5	5		T31	1		T2	164
valid_sources[0x4c]	16809	1			T5	3		T31	2		T20	7
valid_sources[0x4d]	17315	1			T32	1		T21	4		T2	205
valid_sources[0x4e]	19361	1			T5	1		T26	1		T21	1
valid_sources[0x4f]	15153	1			T5	1		T26	1		T30	2
valid_sources[0x50]	16573	1			T5	3		T21	1		T2	212
valid_sources[0x51]	17496	1			T32	1		T21	4		T2	204
valid_sources[0x52]	18229	1			T32	1		T2	213		T4	7
valid_sources[0x53]	15636	1			T31	1		T21	1		T2	207
valid_sources[0x54]	16914	1			T5	3		T21	1		T2	190
valid_sources[0x55]	16347	1			T5	4		T32	1		T21	1
valid_sources[0x56]	15584	1			T21	5		T2	181		T25	2
valid_sources[0x57]	16096	1			T5	6		T2	220		T4	5
valid_sources[0x58]	14626	1			T21	2		T2	220		T4	1
valid_sources[0x59]	18320	1			T26	1		T31	1		T21	1
valid_sources[0x5a]	16319	1			T7	1		T5	3		T31	1
valid_sources[0x5b]	15050	1			T2	220		T4	9		T25	2
valid_sources[0x5c]	16201	1			T5	2		T2	208		T4	5
valid_sources[0x5d]	15229	1			T5	3		T21	3		T2	173
valid_sources[0x5e]	16351	1			T5	7		T2	189		T23	1
valid_sources[0x5f]	15812	1			T5	1		T26	2		T32	1
valid_sources[0x60]	15798	1			T5	6		T29	3		T20	7
valid_sources[0x61]	17458	1			T2	210		T4	3		T25	4
valid_sources[0x62]	16117	1			T31	1		T21	1		T2	185
valid_sources[0x63]	16382	1			T7	1		T5	2		T2	229
valid_sources[0x64]	16466	1			T5	1		T30	1		T2	201
valid_sources[0x65]	18335	1			T31	1		T32	1		T21	2
valid_sources[0x66]	15936	1			T5	1		T20	2		T2	197
valid_sources[0x67]	16541	1			T5	8		T2	186		T25	3
valid_sources[0x68]	18204	1			T5	5		T21	2		T2	176
valid_sources[0x69]	17670	1			T5	4		T2	200		T12	348
valid_sources[0x6a]	16238	1			T5	2		T31	1		T21	1
valid_sources[0x6b]	17463	1			T2	202		T4	3		T25	1
valid_sources[0x6c]	17297	1			T21	1		T2	208		T4	6
valid_sources[0x6d]	18429	1			T31	2		T1	1882		T21	2
valid_sources[0x6e]	16700	1			T26	1		T21	1		T2	168
valid_sources[0x6f]	17103	1			T5	3		T21	2		T2	140
valid_sources[0x70]	14668	1			T7	4		T29	2		T21	1
valid_sources[0x71]	14902	1			T26	1		T30	2		T31	1
valid_sources[0x72]	18352	1			T32	1		T2	234		T4	7
valid_sources[0x73]	17057	1			T7	3		T32	1		T21	1
valid_sources[0x74]	17140	1			T5	1		T21	1		T2	167
valid_sources[0x75]	15652	1			T5	1		T31	2		T21	1
valid_sources[0x76]	16341	1			T5	1		T31	1		T21	1
valid_sources[0x77]	15804	1			T5	2		T31	1		T21	1
valid_sources[0x78]	19116	1			T5	4		T31	1		T21	1
valid_sources[0x79]	16923	1			T5	4		T21	2		T2	188
valid_sources[0x7a]	14801	1			T5	2		T21	2		T2	162
valid_sources[0x7b]	16445	1			T5	3		T31	1		T21	1
valid_sources[0x7c]	16474	1			T5	1		T31	1		T21	3
valid_sources[0x7d]	16807	1			T5	3		T31	2		T2	212
valid_sources[0x7e]	15865	1			T5	1		T31	1		T21	2
valid_sources[0x7f]	16430	1			T2	200		T4	1		T25	1
valid_sources[0x80]	16798	1			T21	4		T2	177		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

899592

1

T7

15

T5

27

T26

5

values[0x0]

all_enables

biggest_size

1359748

1

T7

4

T5

126

T26

3

values[0x1]

all_enables

biggest_size

1309325

1

T7

5

T5

70

T26

1