Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T27
0	1	Covered	T5,T30,T1
1	0	Covered	T7,T5,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T30,T1
1	0	Covered	T8,T27,T36
1	1	Covered	T7,T5,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1194326376	14783	0	0
GateOpen_A	1194326376	20969	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194326376	14783	0	0
T1	0	78	0	0
T2	0	82	0	0
T5	401911	47	0	0
T6	239891	0	0	0
T8	5560	17	0	0
T20	0	4	0	0
T21	0	16	0	0
T26	3934	0	0	0
T27	8696	4	0	0
T28	4323	0	0	0
T29	10265	0	0	0
T30	3103	22	0	0
T31	11251	0	0	0
T32	47062	0	0	0
T36	0	25	0	0
T159	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194326376	20969	0	0
T1	0	94	0	0
T5	401911	59	0	0
T6	239891	4	0	0
T8	5560	21	0	0
T20	0	8	0	0
T21	0	16	0	0
T26	3934	0	0	0
T27	8696	8	0	0
T28	4323	0	0	0
T29	10265	4	0	0
T30	3103	26	0	0
T31	11251	0	0	0
T32	47062	0	0	0
T36	0	29	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T27
0	1	Covered	T5,T30,T1
1	0	Covered	T7,T5,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T30,T1
1	0	Covered	T8,T27,T36
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	133325221	3480	0	0
GateOpen_A	133325221	5025	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133325221	3480	0	0
T1	0	19	0	0
T2	0	19	0	0
T5	43068	10	0	0
T6	25684	0	0	0
T8	608	4	0	0
T20	0	1	0	0
T21	0	3	0	0
T26	438	0	0	0
T27	963	1	0	0
T28	458	0	0	0
T29	1123	0	0	0
T30	334	4	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	0	7	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133325221	5025	0	0
T1	0	23	0	0
T5	43068	13	0	0
T6	25684	1	0	0
T8	608	5	0	0
T20	0	2	0	0
T21	0	3	0	0
T26	438	0	0	0
T27	963	2	0	0
T28	458	0	0	0
T29	1123	1	0	0
T30	334	5	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T27
0	1	Covered	T5,T30,T1
1	0	Covered	T7,T5,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T30,T1
1	0	Covered	T8,T27,T36
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	266651436	3773	0	0
GateOpen_A	266651436	5318	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266651436	3773	0	0
T1	0	21	0	0
T2	0	19	0	0
T5	86135	13	0	0
T6	51367	0	0	0
T8	1216	4	0	0
T20	0	1	0	0
T21	0	4	0	0
T26	877	0	0	0
T27	1926	1	0	0
T28	916	0	0	0
T29	2246	0	0	0
T30	668	6	0	0
T31	2750	0	0	0
T32	11963	0	0	0
T36	0	7	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266651436	5318	0	0
T1	0	25	0	0
T5	86135	16	0	0
T6	51367	1	0	0
T8	1216	5	0	0
T20	0	2	0	0
T21	0	4	0	0
T26	877	0	0	0
T27	1926	2	0	0
T28	916	0	0	0
T29	2246	1	0	0
T30	668	7	0	0
T31	2750	0	0	0
T32	11963	0	0	0
T36	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T27
0	1	Covered	T5,T30,T1
1	0	Covered	T7,T5,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T30,T1
1	0	Covered	T8,T27,T36
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	525732919	3748	0	0
GateOpen_A	525732919	5296	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525732919	3748	0	0
T1	0	19	0	0
T2	0	20	0	0
T5	172203	11	0	0
T6	102798	0	0	0
T8	2496	4	0	0
T20	0	1	0	0
T21	0	4	0	0
T26	1746	0	0	0
T27	3876	1	0	0
T28	1966	0	0	0
T29	4597	0	0	0
T30	1400	6	0	0
T31	4751	0	0	0
T32	19412	0	0	0
T36	0	7	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525732919	5296	0	0
T1	0	23	0	0
T5	172203	14	0	0
T6	102798	1	0	0
T8	2496	5	0	0
T20	0	2	0	0
T21	0	4	0	0
T26	1746	0	0	0
T27	3876	2	0	0
T28	1966	0	0	0
T29	4597	1	0	0
T30	1400	7	0	0
T31	4751	0	0	0
T32	19412	0	0	0
T36	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T27
0	1	Covered	T5,T30,T1
1	0	Covered	T7,T5,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T30,T1
1	0	Covered	T8,T27,T36
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	268616800	3782	0	0
GateOpen_A	268616800	5330	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268616800	3782	0	0
T1	0	19	0	0
T2	0	24	0	0
T5	100505	13	0	0
T6	60042	0	0	0
T8	1240	5	0	0
T20	0	1	0	0
T21	0	5	0	0
T26	873	0	0	0
T27	1931	1	0	0
T28	983	0	0	0
T29	2299	0	0	0
T30	701	6	0	0
T31	2376	0	0	0
T32	9707	0	0	0
T36	0	4	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268616800	5330	0	0
T1	0	23	0	0
T5	100505	16	0	0
T6	60042	1	0	0
T8	1240	6	0	0
T20	0	2	0	0
T21	0	5	0	0
T26	873	0	0	0
T27	1931	2	0	0
T28	983	0	0	0
T29	2299	1	0	0
T30	701	7	0	0
T31	2376	0	0	0
T32	9707	0	0	0
T36	0	5	0	0