Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_div2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_div2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_storage_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_step_down_acks_sync.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_send.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_send.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_main_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_main_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_main_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_main_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T1,T21 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T1,T21 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T1,T21 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T1,T21 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_usb_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_status.u_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_usb_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_usb_status.u_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_ref_meas_en_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_ref_meas_en_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.ack_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.ack_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_out.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T5,T8 |
| 0 |
Covered |
T7,T5,T8 |