Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	808061870	69151	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808061870	69151	0	0
T1	904460	194	0	0
T2	918525	1416	0	0
T3	0	290	0	0
T4	132465	0	0	0
T12	0	1393	0	0
T13	0	546	0	0
T14	0	287	0	0
T15	0	195	0	0
T16	0	712	0	0
T17	0	94	0	0
T18	0	300	0	0
T19	8045	0	0	0
T20	9935	0	0	0
T21	127250	0	0	0
T22	6800	0	0	0
T23	9830	0	0	0
T24	8210	0	0	0
T25	71575	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161612374	10398	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	10398	0	0
T1	180892	32	0	0
T2	183705	197	0	0
T3	0	38	0	0
T4	26493	0	0	0
T12	0	266	0	0
T13	0	75	0	0
T14	0	45	0	0
T15	0	32	0	0
T16	0	112	0	0
T17	0	13	0	0
T18	0	45	0	0
T19	1609	0	0	0
T20	1987	0	0	0
T21	25450	0	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161612374	10274	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	10274	0	0
T1	180892	30	0	0
T2	183705	194	0	0
T3	0	38	0	0
T4	26493	0	0	0
T12	0	266	0	0
T13	0	76	0	0
T14	0	45	0	0
T15	0	32	0	0
T16	0	112	0	0
T17	0	14	0	0
T18	0	44	0	0
T19	1609	0	0	0
T20	1987	0	0	0
T21	25450	0	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161612374	13997	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	13997	0	0
T1	180892	39	0	0
T2	183705	286	0	0
T3	0	58	0	0
T4	26493	0	0	0
T12	0	266	0	0
T13	0	109	0	0
T14	0	59	0	0
T15	0	40	0	0
T16	0	142	0	0
T17	0	19	0	0
T18	0	60	0	0
T19	1609	0	0	0
T20	1987	0	0	0
T21	25450	0	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161612374	13883	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	13883	0	0
T1	180892	40	0	0
T2	183705	288	0	0
T3	0	59	0	0
T4	26493	0	0	0
T12	0	266	0	0
T13	0	107	0	0
T14	0	58	0	0
T15	0	40	0	0
T16	0	142	0	0
T17	0	19	0	0
T18	0	61	0	0
T19	1609	0	0	0
T20	1987	0	0	0
T21	25450	0	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161612374	20599	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	20599	0	0
T1	180892	53	0	0
T2	183705	451	0	0
T3	0	97	0	0
T4	26493	0	0	0
T12	0	329	0	0
T13	0	179	0	0
T14	0	80	0	0
T15	0	51	0	0
T16	0	204	0	0
T17	0	29	0	0
T18	0	90	0	0
T19	1609	0	0	0
T20	1987	0	0	0
T21	25450	0	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0