Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_io_step_down_req_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_step_down_req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_io_div4_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_main_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div2_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div4_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_usb_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_io_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_step_down_req_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync

Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Cond Coverage for Module : prim_mubi4_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

Branch Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 22540 22540 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 969674244 954491346 0 14490
gen_flops.gen_stable_chks.OutputDelay_A 2147483647 2147483647 0 16905
gen_flops.gen_stable_chks.OutputIfUnstable_A 2147483647 208369 0 0
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22540 22540 0 0
T5 28 28 0 0
T6 28 28 0 0
T7 28 28 0 0
T8 28 28 0 0
T26 28 28 0 0
T27 28 28 0 0
T28 28 28 0 0
T29 28 28 0 0
T30 28 28 0 0
T31 28 28 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T5 3200390 3190949 0 0
T6 1922627 1920924 0 0
T7 144643 142171 0 0
T8 48906 46048 0 0
T26 46458 42684 0 0
T27 62024 59886 0 0
T28 53369 46529 0 0
T29 74033 71338 0 0
T30 38035 33000 0 0
T31 95176 91039 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 969674244 954491346 0 14490
T5 341070 339972 0 18
T6 125226 125088 0 18
T7 12468 12210 0 18
T8 8220 7698 0 18
T26 10470 9558 0 18
T27 5862 5604 0 18
T28 12282 10566 0 18
T29 6888 6588 0 18
T30 8748 7458 0 18
T31 14844 14106 0 18

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 16905
T5 1099425 1095557 0 21
T6 716872 716116 0 21
T7 51033 50024 0 21
T8 14868 13841 0 21
T26 12503 11419 0 21
T27 21730 20791 0 21
T28 14248 12257 0 21
T29 26049 24957 0 21
T30 10148 8652 0 21
T31 29494 28043 0 21

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 208369 0 0
T1 0 209 0 0
T2 0 527 0 0
T5 1099425 167 0 0
T6 716872 4 0 0
T7 51033 200 0 0
T8 14868 40 0 0
T19 0 71 0 0
T23 0 99 0 0
T24 0 80 0 0
T26 12503 72 0 0
T27 21730 28 0 0
T28 14248 12 0 0
T29 26049 12 0 0
T30 10148 52 0 0
T31 29494 230 0 0
T32 0 197 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T5 1759895 1755303 0 0
T6 1080529 1079681 0 0
T7 81142 79898 0 0
T8 25818 24470 0 0
T26 23485 21668 0 0
T27 34432 33452 0 0
T28 26839 23667 0 0
T29 41096 39754 0 0
T30 19139 16851 0 0
T31 50838 48851 0 0

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 525732438 521347555 0 0
gen_flops.gen_stable_chks.OutputDelay_A 525732438 521340925 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 525732438 30170 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732438 521347555 0 0
T5 172203 171534 0 0
T6 102798 102663 0 0
T7 9073 8897 0 0
T8 2496 2334 0 0
T26 1745 1596 0 0
T27 3876 3714 0 0
T28 1966 1694 0 0
T29 4597 4408 0 0
T30 1400 1197 0 0
T31 4750 4520 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732438 521340925 0 2415
T5 172203 171525 0 3
T6 102798 102660 0 3
T7 9073 8894 0 3
T8 2496 2331 0 3
T26 1745 1593 0 3
T27 3876 3711 0 3
T28 1966 1691 0 3
T29 4597 4405 0 3
T30 1400 1194 0 3
T31 4750 4517 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732438 30170 0 0
T1 0 88 0 0
T2 0 226 0 0
T5 172203 10 0 0
T6 102798 0 0 0
T7 9073 45 0 0
T8 2496 0 0 0
T19 0 32 0 0
T23 0 53 0 0
T24 0 30 0 0
T26 1745 18 0 0
T27 3876 0 0 0
T28 1966 0 0 0
T29 4597 0 0 0
T30 1400 0 0 0
T31 4750 68 0 0
T32 0 58 0 0

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_no_flops.OutputDelay_A 161612374 159088689 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_no_flops.OutputDelay_A 161612374 159088689 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_flops.gen_stable_chks.OutputDelay_A 161612374 159081891 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 161612374 18992 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159081891 0 2415
T5 56845 56662 0 3
T6 20871 20848 0 3
T7 2078 2035 0 3
T8 1370 1283 0 3
T26 1745 1593 0 3
T27 977 934 0 3
T28 2047 1761 0 3
T29 1148 1098 0 3
T30 1458 1243 0 3
T31 2474 2351 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 18992 0 0
T1 0 56 0 0
T2 0 135 0 0
T5 56845 6 0 0
T6 20871 0 0 0
T7 2078 44 0 0
T8 1370 0 0 0
T19 0 23 0 0
T23 0 31 0 0
T24 0 20 0 0
T26 1745 14 0 0
T27 977 0 0 0
T28 2047 0 0 0
T29 1148 0 0 0
T30 1458 0 0 0
T31 2474 48 0 0
T32 0 82 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T26

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T26
0 Covered T7,T5,T8


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_flops.gen_stable_chks.OutputDelay_A 161612374 159081891 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 161612374 21349 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159081891 0 2415
T5 56845 56662 0 3
T6 20871 20848 0 3
T7 2078 2035 0 3
T8 1370 1283 0 3
T26 1745 1593 0 3
T27 977 934 0 3
T28 2047 1761 0 3
T29 1148 1098 0 3
T30 1458 1243 0 3
T31 2474 2351 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 21349 0 0
T1 0 65 0 0
T2 0 166 0 0
T5 56845 8 0 0
T6 20871 0 0 0
T7 2078 47 0 0
T8 1370 0 0 0
T19 0 16 0 0
T23 0 15 0 0
T24 0 30 0 0
T26 1745 18 0 0
T27 977 0 0 0
T28 2047 0 0 0
T29 1148 0 0 0
T30 1458 0 0 0
T31 2474 42 0 0
T32 0 57 0 0

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 557232789 0 0
gen_no_flops.OutputDelay_A 559488063 557232789 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 557232789 0 0
T5 203383 203072 0 0
T6 143083 143014 0 0
T7 9451 9339 0 0
T8 2408 2339 0 0
T26 1817 1691 0 0
T27 3975 3949 0 0
T28 2047 1907 0 0
T29 4789 4677 0 0
T30 1458 1389 0 0
T31 4949 4823 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 557232789 0 0
T5 203383 203072 0 0
T6 143083 143014 0 0
T7 9451 9339 0 0
T8 2408 2339 0 0
T26 1817 1691 0 0
T27 3975 3949 0 0
T28 2047 1907 0 0
T29 4789 4677 0 0
T30 1458 1389 0 0
T31 4949 4823 0 0

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 525732438 523568439 0 0
gen_no_flops.OutputDelay_A 525732438 523568439 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732438 523568439 0 0
T5 172203 171904 0 0
T6 102798 102732 0 0
T7 9073 8966 0 0
T8 2496 2430 0 0
T26 1745 1624 0 0
T27 3876 3851 0 0
T28 1966 1831 0 0
T29 4597 4490 0 0
T30 1400 1334 0 0
T31 4750 4629 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732438 523568439 0 0
T5 172203 171904 0 0
T6 102798 102732 0 0
T7 9073 8966 0 0
T8 2496 2430 0 0
T26 1745 1624 0 0
T27 3876 3851 0 0
T28 1966 1831 0 0
T29 4597 4490 0 0
T30 1400 1334 0 0
T31 4750 4629 0 0

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 266651037 266651037 0 0
gen_no_flops.OutputDelay_A 266651037 266651037 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266651037 266651037 0 0
T5 86135 86135 0 0
T6 51366 51366 0 0
T7 5208 5208 0 0
T8 1215 1215 0 0
T26 876 876 0 0
T27 1926 1926 0 0
T28 916 916 0 0
T29 2245 2245 0 0
T30 667 667 0 0
T31 2750 2750 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266651037 266651037 0 0
T5 86135 86135 0 0
T6 51366 51366 0 0
T7 5208 5208 0 0
T8 1215 1215 0 0
T26 876 876 0 0
T27 1926 1926 0 0
T28 916 916 0 0
T29 2245 2245 0 0
T30 667 667 0 0
T31 2750 2750 0 0

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 133324836 133324836 0 0
gen_no_flops.OutputDelay_A 133324836 133324836 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133324836 133324836 0 0
T5 43067 43067 0 0
T6 25683 25683 0 0
T7 2602 2602 0 0
T8 608 608 0 0
T26 437 437 0 0
T27 963 963 0 0
T28 458 458 0 0
T29 1123 1123 0 0
T30 334 334 0 0
T31 1374 1374 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133324836 133324836 0 0
T5 43067 43067 0 0
T6 25683 25683 0 0
T7 2602 2602 0 0
T8 608 608 0 0
T26 437 437 0 0
T27 963 963 0 0
T28 458 458 0 0
T29 1123 1123 0 0
T30 334 334 0 0
T31 1374 1374 0 0

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 268616400 267527104 0 0
gen_no_flops.OutputDelay_A 268616400 267527104 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 268616400 267527104 0 0
T5 100505 100355 0 0
T6 60041 60008 0 0
T7 4536 4483 0 0
T8 1239 1206 0 0
T26 872 812 0 0
T27 1930 1917 0 0
T28 982 915 0 0
T29 2298 2245 0 0
T30 700 667 0 0
T31 2375 2315 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 268616400 267527104 0 0
T5 100505 100355 0 0
T6 60041 60008 0 0
T7 4536 4483 0 0
T8 1239 1206 0 0
T26 872 812 0 0
T27 1930 1917 0 0
T28 982 915 0 0
T29 2298 2245 0 0
T30 700 667 0 0
T31 2375 2315 0 0

Line Coverage for Instance : tb.dut.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6


Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 161612374 159081891 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159081891 0 2415
T5 56845 56662 0 3
T6 20871 20848 0 3
T7 2078 2035 0 3
T8 1370 1283 0 3
T26 1745 1593 0 3
T27 977 934 0 3
T28 2047 1761 0 3
T29 1148 1098 0 3
T30 1458 1243 0 3
T31 2474 2351 0 3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 161612374 159081891 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159081891 0 2415
T5 56845 56662 0 3
T6 20871 20848 0 3
T7 2078 2035 0 3
T8 1370 1283 0 3
T26 1745 1593 0 3
T27 977 934 0 3
T28 2047 1761 0 3
T29 1148 1098 0 3
T30 1458 1243 0 3
T31 2474 2351 0 3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 161612374 159081891 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159081891 0 2415
T5 56845 56662 0 3
T6 20871 20848 0 3
T7 2078 2035 0 3
T8 1370 1283 0 3
T26 1745 1593 0 3
T27 977 934 0 3
T28 2047 1761 0 3
T29 1148 1098 0 3
T30 1458 1243 0 3
T31 2474 2351 0 3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 161612374 159081891 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159081891 0 2415
T5 56845 56662 0 3
T6 20871 20848 0 3
T7 2078 2035 0 3
T8 1370 1283 0 3
T26 1745 1593 0 3
T27 977 934 0 3
T28 2047 1761 0 3
T29 1148 1098 0 3
T30 1458 1243 0 3
T31 2474 2351 0 3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 161612374 159081891 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159081891 0 2415
T5 56845 56662 0 3
T6 20871 20848 0 3
T7 2078 2035 0 3
T8 1370 1283 0 3
T26 1745 1593 0 3
T27 977 934 0 3
T28 2047 1761 0 3
T29 1148 1098 0 3
T30 1458 1243 0 3
T31 2474 2351 0 3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 161612374 159081891 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159081891 0 2415
T5 56845 56662 0 3
T6 20871 20848 0 3
T7 2078 2035 0 3
T8 1370 1283 0 3
T26 1745 1593 0 3
T27 977 934 0 3
T28 2047 1761 0 3
T29 1148 1098 0 3
T30 1458 1243 0 3
T31 2474 2351 0 3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_no_flops.OutputDelay_A 161612374 159088689 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_no_flops.OutputDelay_A 161612374 159088689 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_no_flops.OutputDelay_A 161612374 159088689 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161612374 159088689 0 0
gen_no_flops.OutputDelay_A 161612374 159088689 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161612374 159088689 0 0
T5 56845 56671 0 0
T6 20871 20851 0 0
T7 2078 2038 0 0
T8 1370 1286 0 0
T26 1745 1596 0 0
T27 977 937 0 0
T28 2047 1764 0 0
T29 1148 1101 0 0
T30 1458 1246 0 0
T31 2474 2354 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 554908003 0 0
gen_flops.gen_stable_chks.OutputDelay_A 559488063 554901295 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 559488063 34057 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554901295 0 2415
T5 203383 202677 0 3
T6 143083 142940 0 3
T7 9451 9265 0 3
T8 2408 2236 0 3
T26 1817 1660 0 3
T27 3975 3803 0 3
T28 2047 1761 0 3
T29 4789 4589 0 3
T30 1458 1243 0 3
T31 4949 4706 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 34057 0 0
T5 203383 30 0 0
T6 143083 1 0 0
T7 9451 20 0 0
T8 2408 9 0 0
T26 1817 10 0 0
T27 3975 5 0 0
T28 2047 3 0 0
T29 4789 3 0 0
T30 1458 13 0 0
T31 4949 19 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 554908003 0 0
gen_no_flops.OutputDelay_A 559488063 554908003 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 554908003 0 0
gen_flops.gen_stable_chks.OutputDelay_A 559488063 554901295 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 559488063 34494 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554901295 0 2415
T5 203383 202677 0 3
T6 143083 142940 0 3
T7 9451 9265 0 3
T8 2408 2236 0 3
T26 1817 1660 0 3
T27 3975 3803 0 3
T28 2047 1761 0 3
T29 4789 4589 0 3
T30 1458 1243 0 3
T31 4949 4706 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 34494 0 0
T5 203383 41 0 0
T6 143083 1 0 0
T7 9451 16 0 0
T8 2408 13 0 0
T26 1817 4 0 0
T27 3975 9 0 0
T28 2047 3 0 0
T29 4789 3 0 0
T30 1458 17 0 0
T31 4949 21 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 554908003 0 0
gen_no_flops.OutputDelay_A 559488063 554908003 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 554908003 0 0
gen_flops.gen_stable_chks.OutputDelay_A 559488063 554901295 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 559488063 34713 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554901295 0 2415
T5 203383 202677 0 3
T6 143083 142940 0 3
T7 9451 9265 0 3
T8 2408 2236 0 3
T26 1817 1660 0 3
T27 3975 3803 0 3
T28 2047 1761 0 3
T29 4789 4589 0 3
T30 1458 1243 0 3
T31 4949 4706 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 34713 0 0
T5 203383 41 0 0
T6 143083 1 0 0
T7 9451 16 0 0
T8 2408 9 0 0
T26 1817 4 0 0
T27 3975 5 0 0
T28 2047 3 0 0
T29 4789 3 0 0
T30 1458 9 0 0
T31 4949 17 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 554908003 0 0
gen_no_flops.OutputDelay_A 559488063 554908003 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT7,T5,T8
1CoveredT7,T5,T8

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T7,T5,T8
0 Covered T7,T5,T8


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 554908003 0 0
gen_flops.gen_stable_chks.OutputDelay_A 559488063 554901295 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 559488063 34594 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554901295 0 2415
T5 203383 202677 0 3
T6 143083 142940 0 3
T7 9451 9265 0 3
T8 2408 2236 0 3
T26 1817 1660 0 3
T27 3975 3803 0 3
T28 2047 1761 0 3
T29 4789 4589 0 3
T30 1458 1243 0 3
T31 4949 4706 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 34594 0 0
T5 203383 31 0 0
T6 143083 1 0 0
T7 9451 12 0 0
T8 2408 9 0 0
T26 1817 4 0 0
T27 3975 9 0 0
T28 2047 3 0 0
T29 4789 3 0 0
T30 1458 13 0 0
T31 4949 15 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 559488063 554908003 0 0
gen_no_flops.OutputDelay_A 559488063 554908003 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 559488063 554908003 0 0
T5 203383 202686 0 0
T6 143083 142943 0 0
T7 9451 9268 0 0
T8 2408 2239 0 0
T26 1817 1663 0 0
T27 3975 3806 0 0
T28 2047 1764 0 0
T29 4789 4592 0 0
T30 1458 1246 0 0
T31 4949 4709 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%