Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T1,T21

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	161612374	158941189	0	0
AllClkBypReqTrue_A	161612374	145290	0	0
IoClkBypReqFalse_A	161612374	158852136	0	2415
IoClkBypReqTrue_A	161612374	229923	0	0
LcClkBypAckFalse_A	161612374	158950294	0	0
LcClkBypAckTrue_A	161612374	136185	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	158941189	0	0
T5	56845	56608	0	0
T6	20871	20850	0	0
T7	2078	1709	0	0
T8	1370	1285	0	0
T26	1745	1447	0	0
T27	977	936	0	0
T28	2047	1763	0	0
T29	1148	1100	0	0
T30	1458	1245	0	0
T31	2474	2005	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	145290	0	0
T1	0	268	0	0
T2	0	1519	0	0
T5	56845	60	0	0
T6	20871	0	0	0
T7	2078	328	0	0
T8	1370	0	0	0
T19	0	138	0	0
T23	0	21	0	0
T24	0	164	0	0
T26	1745	148	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	348	0	0
T32	0	396	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	158852136	0	2415
T5	56845	56597	0	3
T6	20871	20848	0	3
T7	2078	1641	0	3
T8	1370	1283	0	3
T26	1745	1456	0	3
T27	977	934	0	3
T28	2047	1761	0	3
T29	1148	1098	0	3
T30	1458	1243	0	3
T31	2474	1746	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	229923	0	0
T1	0	441	0	0
T2	0	1780	0	0
T5	56845	65	0	0
T6	20871	0	0	0
T7	2078	394	0	0
T8	1370	0	0	0
T19	0	278	0	0
T23	0	472	0	0
T24	0	252	0	0
T26	1745	137	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	605	0	0
T32	0	511	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	158950294	0	0
T5	56845	56608	0	0
T6	20871	20850	0	0
T7	2078	1820	0	0
T8	1370	1285	0	0
T26	1745	1499	0	0
T27	977	936	0	0
T28	2047	1763	0	0
T29	1148	1100	0	0
T30	1458	1245	0	0
T31	2474	1933	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	136185	0	0
T1	0	235	0	0
T2	0	1246	0	0
T5	56845	60	0	0
T6	20871	0	0	0
T7	2078	217	0	0
T8	1370	0	0	0
T19	0	195	0	0
T23	0	159	0	0
T24	0	156	0	0
T26	1745	96	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	420	0	0
T32	0	260	0	0