Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16285	0	0
TransStop_A	2147483647	8482	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16285	0	0
T1	0	47	0	0
T2	0	120	0	0
T5	813532	4	0	0
T6	572336	0	0	0
T8	9632	0	0	0
T12	0	795	0	0
T13	0	261	0	0
T20	0	4	0	0
T26	7272	0	0	0
T27	15904	0	0	0
T28	8192	0	0	0
T29	19156	0	0	0
T30	5836	0	0	0
T31	19796	0	0	0
T32	80888	0	0	0
T33	0	4	0	0
T109	0	34	0	0
T110	0	4	0	0
T111	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8482	0	0
T1	0	19	0	0
T2	0	51	0	0
T5	813532	4	0	0
T6	572336	0	0	0
T8	9632	0	0	0
T12	0	377	0	0
T13	0	158	0	0
T14	0	36	0	0
T20	0	4	0	0
T26	7272	0	0	0
T27	15904	0	0	0
T28	8192	0	0	0
T29	19156	0	0	0
T30	5836	0	0	0
T31	19796	0	0	0
T32	80888	0	0	0
T109	0	11	0	0
T110	0	4	0	0
T111	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	559488529	4045	0	0
TransStop_A	559488529	2097	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488529	4045	0	0
T1	0	13	0	0
T2	0	30	0	0
T5	203383	1	0	0
T6	143084	0	0	0
T8	2408	0	0	0
T12	0	185	0	0
T13	0	62	0	0
T20	0	1	0	0
T26	1818	0	0	0
T27	3976	0	0	0
T28	2048	0	0	0
T29	4789	0	0	0
T30	1459	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T109	0	10	0	0
T110	0	1	0	0
T111	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488529	2097	0	0
T1	0	5	0	0
T2	0	14	0	0
T5	203383	1	0	0
T6	143084	0	0	0
T8	2408	0	0	0
T12	0	86	0	0
T13	0	40	0	0
T14	0	10	0	0
T20	0	1	0	0
T26	1818	0	0	0
T27	3976	0	0	0
T28	2048	0	0	0
T29	4789	0	0	0
T30	1459	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T109	0	3	0	0
T110	0	1	0	0
T111	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	559488529	4080	0	0
TransStop_A	559488529	2113	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488529	4080	0	0
T1	0	12	0	0
T2	0	35	0	0
T5	203383	1	0	0
T6	143084	0	0	0
T8	2408	0	0	0
T12	0	209	0	0
T13	0	72	0	0
T20	0	1	0	0
T26	1818	0	0	0
T27	3976	0	0	0
T28	2048	0	0	0
T29	4789	0	0	0
T30	1459	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T109	0	8	0	0
T110	0	1	0	0
T111	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488529	2113	0	0
T1	0	5	0	0
T2	0	15	0	0
T5	203383	1	0	0
T6	143084	0	0	0
T8	2408	0	0	0
T12	0	104	0	0
T13	0	41	0	0
T14	0	7	0	0
T20	0	1	0	0
T26	1818	0	0	0
T27	3976	0	0	0
T28	2048	0	0	0
T29	4789	0	0	0
T30	1459	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	559488529	4070	0	0
TransStop_A	559488529	2130	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488529	4070	0	0
T1	0	11	0	0
T2	0	28	0	0
T5	203383	1	0	0
T6	143084	0	0	0
T8	2408	0	0	0
T12	0	209	0	0
T13	0	68	0	0
T20	0	1	0	0
T26	1818	0	0	0
T27	3976	0	0	0
T28	2048	0	0	0
T29	4789	0	0	0
T30	1459	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T109	0	6	0	0
T110	0	1	0	0
T111	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488529	2130	0	0
T1	0	5	0	0
T2	0	12	0	0
T5	203383	1	0	0
T6	143084	0	0	0
T8	2408	0	0	0
T12	0	98	0	0
T13	0	38	0	0
T14	0	10	0	0
T20	0	1	0	0
T26	1818	0	0	0
T27	3976	0	0	0
T28	2048	0	0	0
T29	4789	0	0	0
T30	1459	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	559488529	4090	0	0
TransStop_A	559488529	2142	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488529	4090	0	0
T1	0	11	0	0
T2	0	27	0	0
T5	203383	1	0	0
T6	143084	0	0	0
T8	2408	0	0	0
T12	0	192	0	0
T13	0	59	0	0
T20	0	1	0	0
T26	1818	0	0	0
T27	3976	0	0	0
T28	2048	0	0	0
T29	4789	0	0	0
T30	1459	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T109	0	10	0	0
T110	0	1	0	0
T111	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488529	2142	0	0
T1	0	4	0	0
T2	0	10	0	0
T5	203383	1	0	0
T6	143084	0	0	0
T8	2408	0	0	0
T12	0	89	0	0
T13	0	39	0	0
T14	0	9	0	0
T20	0	1	0	0
T26	1818	0	0	0
T27	3976	0	0	0
T28	2048	0	0	0
T29	4789	0	0	0
T30	1459	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T109	0	4	0	0
T110	0	1	0	0
T111	0	1	0	0