SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 323224748 | 318177378 | 0 | 0 |
gen_flops.OutputDelay_A | 323224748 | 318163782 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T26 | 2 | 2 | 0 | 0 |
T27 | 2 | 2 | 0 | 0 |
T28 | 2 | 2 | 0 | 0 |
T29 | 2 | 2 | 0 | 0 |
T30 | 2 | 2 | 0 | 0 |
T31 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 323224748 | 318177378 | 0 | 0 |
T5 | 113690 | 113342 | 0 | 0 |
T6 | 41742 | 41702 | 0 | 0 |
T7 | 4156 | 4076 | 0 | 0 |
T8 | 2740 | 2572 | 0 | 0 |
T26 | 3490 | 3192 | 0 | 0 |
T27 | 1954 | 1874 | 0 | 0 |
T28 | 4094 | 3528 | 0 | 0 |
T29 | 2296 | 2202 | 0 | 0 |
T30 | 2916 | 2492 | 0 | 0 |
T31 | 4948 | 4708 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 323224748 | 318163782 | 0 | 4830 |
T5 | 113690 | 113324 | 0 | 6 |
T6 | 41742 | 41696 | 0 | 6 |
T7 | 4156 | 4070 | 0 | 6 |
T8 | 2740 | 2566 | 0 | 6 |
T26 | 3490 | 3186 | 0 | 6 |
T27 | 1954 | 1868 | 0 | 6 |
T28 | 4094 | 3522 | 0 | 6 |
T29 | 2296 | 2196 | 0 | 6 |
T30 | 2916 | 2486 | 0 | 6 |
T31 | 4948 | 4702 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 161612374 | 159088689 | 0 | 0 |
gen_flops.OutputDelay_A | 161612374 | 159081891 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161612374 | 159088689 | 0 | 0 |
T5 | 56845 | 56671 | 0 | 0 |
T6 | 20871 | 20851 | 0 | 0 |
T7 | 2078 | 2038 | 0 | 0 |
T8 | 1370 | 1286 | 0 | 0 |
T26 | 1745 | 1596 | 0 | 0 |
T27 | 977 | 937 | 0 | 0 |
T28 | 2047 | 1764 | 0 | 0 |
T29 | 1148 | 1101 | 0 | 0 |
T30 | 1458 | 1246 | 0 | 0 |
T31 | 2474 | 2354 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161612374 | 159081891 | 0 | 2415 |
T5 | 56845 | 56662 | 0 | 3 |
T6 | 20871 | 20848 | 0 | 3 |
T7 | 2078 | 2035 | 0 | 3 |
T8 | 1370 | 1283 | 0 | 3 |
T26 | 1745 | 1593 | 0 | 3 |
T27 | 977 | 934 | 0 | 3 |
T28 | 2047 | 1761 | 0 | 3 |
T29 | 1148 | 1098 | 0 | 3 |
T30 | 1458 | 1243 | 0 | 3 |
T31 | 2474 | 2351 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 161612374 | 159088689 | 0 | 0 |
gen_flops.OutputDelay_A | 161612374 | 159081891 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161612374 | 159088689 | 0 | 0 |
T5 | 56845 | 56671 | 0 | 0 |
T6 | 20871 | 20851 | 0 | 0 |
T7 | 2078 | 2038 | 0 | 0 |
T8 | 1370 | 1286 | 0 | 0 |
T26 | 1745 | 1596 | 0 | 0 |
T27 | 977 | 937 | 0 | 0 |
T28 | 2047 | 1764 | 0 | 0 |
T29 | 1148 | 1101 | 0 | 0 |
T30 | 1458 | 1246 | 0 | 0 |
T31 | 2474 | 2354 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161612374 | 159081891 | 0 | 2415 |
T5 | 56845 | 56662 | 0 | 3 |
T6 | 20871 | 20848 | 0 | 3 |
T7 | 2078 | 2035 | 0 | 3 |
T8 | 1370 | 1283 | 0 | 3 |
T26 | 1745 | 1593 | 0 | 3 |
T27 | 977 | 934 | 0 | 3 |
T28 | 2047 | 1761 | 0 | 3 |
T29 | 1148 | 1098 | 0 | 3 |
T30 | 1458 | 1243 | 0 | 3 |
T31 | 2474 | 2351 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |