Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
46 |
46 |
100.00 |
Total Bits 0->1 |
23 |
23 |
100.00 |
Total Bits 1->0 |
23 |
23 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
46 |
46 |
100.00 |
Port Bits 0->1 |
23 |
23 |
100.00 |
Port Bits 1->0 |
23 |
23 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T7,T5,T8 |
Yes |
T7,T5,T8 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T1,T21 |
Yes |
T7,T5,T8 |
INPUT |
oh_i[2:0] |
Yes |
Yes |
*T28,*T29,*T22 |
Yes |
T28,T29,T22 |
INPUT |
oh_i[3] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[7:4] |
Yes |
Yes |
*T47,*T48,*T37 |
Yes |
T47,T48,T37 |
INPUT |
oh_i[8] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[20:9] |
Yes |
Yes |
T5,T6,T1 |
Yes |
T5,T6,T1 |
INPUT |
oh_i[21] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
addr_i[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T7,T5,T26 |
Yes |
T7,T5,T26 |
INPUT |
err_o |
Yes |
Yes |
T47,T48,T37 |
Yes |
T47,T48,T37 |
OUTPUT |
*Tests covering at least one bit in the range