Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	161612374	18399617	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	18399617	0	58
T1	180892	14630	0	1
T2	183705	291476	0	0
T3	0	35903	0	1
T4	26493	0	0	0
T12	0	730149	0	0
T13	0	53441	0	0
T14	0	19543	0	0
T15	0	13425	0	0
T16	0	54527	0	0
T17	0	13208	0	0
T19	1609	0	0	0
T20	1987	0	0	0
T21	25450	728	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0
T112	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1
T115	0	0	0	1
T116	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1
T119	0	0	0	1