Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	162485875	5212457	0	0
clk_enables_rd_A	162485875	45320	0	0
clk_hints_rd_A	162485875	40930	0	0
extclk_ctrl_rd_A	162485875	51487	0	0
extclk_ctrl_regwen_rd_A	162485875	38002	0	0
jitter_enable_rd_A	162485875	57308	0	0
jitter_regwen_rd_A	162485875	42677	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	5212457	0	0
T2	183705	61483	0	0
T3	240559	0	0	0
T4	26493	0	0	0
T12	0	126958	0	0
T13	0	157346	0	0
T18	0	37145	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0
T34	0	156155	0	0
T67	0	114621	0	0
T68	0	185872	0	0
T69	0	144031	0	0
T70	0	188697	0	0
T71	0	127356	0	0
T72	2072	0	0	0
T73	1663	0	0	0
T74	1958	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	45320	0	0
T12	402112	2546	0	0
T13	327812	0	0	0
T35	0	10	0	0
T69	0	5722	0	0
T75	241976	0	0	0
T110	1967	0	0	0
T111	1722	0	0	0
T117	0	8	0	0
T134	0	9	0	0
T135	0	10	0	0
T136	0	3115	0	0
T137	0	3131	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	1039	0	0	0
T141	1514	0	0	0
T142	1545	0	0	0
T143	1623	0	0	0
T144	2183	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	40930	0	0
T2	183705	0	0	0
T4	26493	0	0	0
T12	0	2281	0	0
T20	1987	7	0	0
T21	25450	0	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0
T33	0	2	0	0
T69	0	4677	0	0
T72	2072	0	0	0
T73	1663	0	0	0
T117	0	7	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	0	2782	0	0
T137	0	2674	0	0
T145	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	51487	0	0
T1	180892	0	0	0
T2	183705	0	0	0
T12	0	2859	0	0
T19	1609	17	0	0
T20	1987	0	0	0
T21	25450	0	0	0
T22	1360	0	0	0
T23	1966	54	0	0
T31	2474	45	0	0
T32	2021	0	0	0
T33	0	33	0	0
T36	1007	0	0	0
T72	0	46	0	0
T144	0	9	0	0
T146	0	44	0	0
T147	0	37	0	0
T148	0	3	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	38002	0	0
T12	402112	2193	0	0
T13	327812	0	0	0
T45	0	62	0	0
T69	0	4710	0	0
T75	241976	0	0	0
T110	1967	0	0	0
T111	1722	0	0	0
T136	0	2613	0	0
T137	0	2501	0	0
T140	1039	0	0	0
T141	1514	0	0	0
T142	1545	0	0	0
T143	1623	0	0	0
T144	2183	0	0	0
T149	0	26	0	0
T150	0	44	0	0
T151	0	39	0	0
T152	0	27	0	0
T153	0	4741	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	57308	0	0
T2	183705	0	0	0
T4	26493	0	0	0
T12	0	3652	0	0
T20	1987	70	0	0
T21	25450	0	0	0
T22	1360	0	0	0
T23	1966	0	0	0
T24	1642	0	0	0
T25	14315	0	0	0
T33	0	111	0	0
T69	0	6578	0	0
T72	2072	0	0	0
T73	1663	0	0	0
T117	0	247	0	0
T134	0	147	0	0
T135	0	146	0	0
T136	0	3837	0	0
T137	0	4079	0	0
T145	0	193	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	42677	0	0
T12	402112	2456	0	0
T13	327812	0	0	0
T69	0	5447	0	0
T75	241976	0	0	0
T110	1967	0	0	0
T111	1722	0	0	0
T136	0	2890	0	0
T137	0	2988	0	0
T140	1039	0	0	0
T141	1514	0	0	0
T142	1545	0	0	0
T143	1623	0	0	0
T144	2183	0	0	0
T153	0	5413	0	0
T154	0	1228	0	0
T155	0	5720	0	0
T156	0	2117	0	0
T157	0	2163	0	0
T158	0	4620	0	0