Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T2,T4,T25
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1624858750	1377614	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1624858750	294118	0	0
SrcBusyKnown_A	1624858750	1598641200	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1624858750	1377614	0	0
T1	0	3854	0	0
T2	0	22885	0	0
T3	0	3468	0	0
T4	0	1631	0	0
T5	568450	1224	0	0
T6	208710	704	0	0
T8	13700	0	0	0
T12	0	21244	0	0
T21	0	796	0	0
T25	0	1203	0	0
T26	17450	0	0	0
T27	9770	0	0	0
T28	20470	0	0	0
T29	11480	0	0	0
T30	14580	0	0	0
T31	24740	0	0	0
T32	20210	0	0	0
T33	0	2518	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T5	1210586	1206628	0	0
T6	765942	765154	0	0
T7	61740	60742	0	0
T8	15932	14964	0	0
T26	11494	10698	0	0
T27	25340	24310	0	0
T28	12738	11152	0	0
T29	30104	29020	0	0
T30	9118	7878	0	0
T31	32396	31062	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1624858750	294118	0	0
T1	0	1120	0	0
T2	0	4240	0	0
T3	0	420	0	0
T4	0	448	0	0
T5	568450	340	0	0
T6	208710	240	0	0
T8	13700	0	0	0
T12	0	8045	0	0
T21	0	280	0	0
T25	0	427	0	0
T26	17450	0	0	0
T27	9770	0	0	0
T28	20470	0	0	0
T29	11480	0	0	0
T30	14580	0	0	0
T31	24740	0	0	0
T32	20210	0	0	0
T33	0	320	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1624858750	1598641200	0	0
T5	568450	566710	0	0
T6	208710	208510	0	0
T7	20780	20380	0	0
T8	13700	12860	0	0
T26	17450	15960	0	0
T27	9770	9370	0	0
T28	20470	17640	0	0
T29	11480	11010	0	0
T30	14580	12460	0	0
T31	24740	23540	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	87370	0	0
DstReqKnown_A	528190255	523614356	0	0
SrcAckBusyChk_A	162485875	26635	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	87370	0	0
T1	0	284	0	0
T2	0	1586	0	0
T3	0	216	0	0
T4	0	84	0	0
T5	56845	91	0	0
T6	20871	61	0	0
T8	1370	0	0	0
T12	0	2011	0	0
T21	0	74	0	0
T25	0	76	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	157	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528190255	523614356	0	0
T5	172203	171534	0	0
T6	102798	102663	0	0
T7	9073	8897	0	0
T8	2496	2334	0	0
T26	1745	1596	0	0
T27	3876	3714	0	0
T28	1966	1694	0	0
T29	4597	4408	0	0
T30	1400	1197	0	0
T31	4750	4520	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	26635	0	0
T1	0	112	0	0
T2	0	421	0	0
T3	0	42	0	0
T4	0	32	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	800	0	0
T21	0	28	0	0
T25	0	30	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	122756	0	0
DstReqKnown_A	267832498	266673561	0	0
SrcAckBusyChk_A	162485875	26635	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	122756	0	0
T1	0	400	0	0
T2	0	2279	0	0
T3	0	345	0	0
T4	0	116	0	0
T5	56845	125	0	0
T6	20871	67	0	0
T8	1370	0	0	0
T12	0	2011	0	0
T21	0	74	0	0
T25	0	76	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	254	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267832498	266673561	0	0
T5	86135	85949	0	0
T6	51366	51331	0	0
T7	5208	5173	0	0
T8	1215	1167	0	0
T26	876	862	0	0
T27	1926	1857	0	0
T28	916	847	0	0
T29	2245	2204	0	0
T30	667	598	0	0
T31	2750	2695	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	26635	0	0
T1	0	112	0	0
T2	0	421	0	0
T3	0	42	0	0
T4	0	32	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	800	0	0
T21	0	28	0	0
T25	0	30	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	191957	0	0
DstReqKnown_A	133915559	133336175	0	0
SrcAckBusyChk_A	162485875	26635	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	191957	0	0
T1	0	569	0	0
T2	0	3660	0	0
T3	0	601	0	0
T4	0	168	0	0
T5	56845	181	0	0
T6	20871	96	0	0
T8	1370	0	0	0
T12	0	2531	0	0
T21	0	102	0	0
T25	0	106	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	439	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133915559	133336175	0	0
T5	43067	42974	0	0
T6	25683	25666	0	0
T7	2602	2585	0	0
T8	608	584	0	0
T26	437	430	0	0
T27	963	929	0	0
T28	458	424	0	0
T29	1123	1102	0	0
T30	334	300	0	0
T31	1374	1347	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	26635	0	0
T1	0	112	0	0
T2	0	421	0	0
T3	0	42	0	0
T4	0	32	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	800	0	0
T21	0	28	0	0
T25	0	30	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	86371	0	0
DstReqKnown_A	562048397	557269318	0	0
SrcAckBusyChk_A	162485875	26635	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	86371	0	0
T1	0	276	0	0
T2	0	1538	0	0
T3	0	212	0	0
T4	0	84	0	0
T5	56845	88	0	0
T6	20871	61	0	0
T8	1370	0	0	0
T12	0	2011	0	0
T21	0	74	0	0
T25	0	76	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	153	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562048397	557269318	0	0
T5	203383	202686	0	0
T6	143083	142943	0	0
T7	9451	9268	0	0
T8	2408	2239	0	0
T26	1817	1663	0	0
T27	3975	3806	0	0
T28	2047	1764	0	0
T29	4789	4592	0	0
T30	1458	1246	0	0
T31	4949	4709	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	26635	0	0
T1	0	112	0	0
T2	0	421	0	0
T3	0	42	0	0
T4	0	32	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	800	0	0
T21	0	28	0	0
T25	0	30	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	121655	0	0
DstReqKnown_A	269845322	267540359	0	0
SrcAckBusyChk_A	162485875	26126	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	121655	0	0
T1	0	397	0	0
T2	0	2271	0	0
T3	0	350	0	0
T4	0	74	0	0
T5	56845	128	0	0
T6	20871	68	0	0
T8	1370	0	0	0
T12	0	2011	0	0
T21	0	74	0	0
T25	0	54	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	249	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	269845322	267540359	0	0
T5	100505	100171	0	0
T6	60041	59974	0	0
T7	4536	4448	0	0
T8	1239	1158	0	0
T26	872	798	0	0
T27	1930	1849	0	0
T28	982	847	0	0
T29	2298	2204	0	0
T30	700	598	0	0
T31	2375	2260	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	26126	0	0
T1	0	112	0	0
T2	0	421	0	0
T3	0	42	0	0
T4	0	16	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	800	0	0
T21	0	28	0	0
T25	0	15	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T2,T4,T25
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	108334	0	0
DstReqKnown_A	528190255	523614356	0	0
SrcAckBusyChk_A	162485875	32202	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	108334	0	0
T1	0	290	0	0
T2	0	1591	0	0
T3	0	217	0	0
T4	0	164	0	0
T5	56845	95	0	0
T6	20871	61	0	0
T8	1370	0	0	0
T12	0	2025	0	0
T21	0	74	0	0
T25	0	151	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	156	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528190255	523614356	0	0
T5	172203	171534	0	0
T6	102798	102663	0	0
T7	9073	8897	0	0
T8	2496	2334	0	0
T26	1745	1596	0	0
T27	3876	3714	0	0
T28	1966	1694	0	0
T29	4597	4408	0	0
T30	1400	1197	0	0
T31	4750	4520	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	32202	0	0
T1	0	112	0	0
T2	0	427	0	0
T3	0	42	0	0
T4	0	64	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	809	0	0
T21	0	28	0	0
T25	0	60	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T2,T4,T25
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	153622	0	0
DstReqKnown_A	267832498	266673561	0	0
SrcAckBusyChk_A	162485875	32339	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	153622	0	0
T1	0	399	0	0
T2	0	2336	0	0
T3	0	347	0	0
T4	0	228	0	0
T5	56845	122	0	0
T6	20871	69	0	0
T8	1370	0	0	0
T12	0	2025	0	0
T21	0	74	0	0
T25	0	151	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	255	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267832498	266673561	0	0
T5	86135	85949	0	0
T6	51366	51331	0	0
T7	5208	5173	0	0
T8	1215	1167	0	0
T26	876	862	0	0
T27	1926	1857	0	0
T28	916	847	0	0
T29	2245	2204	0	0
T30	667	598	0	0
T31	2750	2695	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	32339	0	0
T1	0	112	0	0
T2	0	427	0	0
T3	0	42	0	0
T4	0	64	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	809	0	0
T21	0	28	0	0
T25	0	60	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T2,T4,T25
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	244163	0	0
DstReqKnown_A	133915559	133336175	0	0
SrcAckBusyChk_A	162485875	32438	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	244163	0	0
T1	0	563	0	0
T2	0	3739	0	0
T3	0	616	0	0
T4	0	328	0	0
T5	56845	182	0	0
T6	20871	93	0	0
T8	1370	0	0	0
T12	0	2569	0	0
T21	0	102	0	0
T25	0	211	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	452	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133915559	133336175	0	0
T5	43067	42974	0	0
T6	25683	25666	0	0
T7	2602	2585	0	0
T8	608	584	0	0
T26	437	430	0	0
T27	963	929	0	0
T28	458	424	0	0
T29	1123	1102	0	0
T30	334	300	0	0
T31	1374	1347	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	32438	0	0
T1	0	112	0	0
T2	0	427	0	0
T3	0	42	0	0
T4	0	64	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	809	0	0
T21	0	28	0	0
T25	0	60	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T2,T4,T25
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	107170	0	0
DstReqKnown_A	562048397	557269318	0	0
SrcAckBusyChk_A	162485875	32325	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	107170	0	0
T1	0	277	0	0
T2	0	1567	0	0
T3	0	215	0	0
T4	0	164	0	0
T5	56845	88	0	0
T6	20871	61	0	0
T8	1370	0	0	0
T12	0	2025	0	0
T21	0	74	0	0
T25	0	151	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	155	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	562048397	557269318	0	0
T5	203383	202686	0	0
T6	143083	142943	0	0
T7	9451	9268	0	0
T8	2408	2239	0	0
T26	1817	1663	0	0
T27	3975	3806	0	0
T28	2047	1764	0	0
T29	4789	4592	0	0
T30	1458	1246	0	0
T31	4949	4709	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	32325	0	0
T1	0	112	0	0
T2	0	427	0	0
T3	0	42	0	0
T4	0	64	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	809	0	0
T21	0	28	0	0
T25	0	60	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Covered	T2,T4,T25
1	0	Covered	T5,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T8
0	1	Unreachable
1	0	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T5,T8
0	1	-	Covered	T5,T6,T1
0	0	1	Covered	T5,T6,T1
0	0	0	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	162485875	154216	0	0
DstReqKnown_A	269845322	267540359	0	0
SrcAckBusyChk_A	162485875	32148	0	0
SrcBusyKnown_A	162485875	159864120	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	154216	0	0
T1	0	399	0	0
T2	0	2318	0	0
T3	0	349	0	0
T4	0	221	0	0
T5	56845	124	0	0
T6	20871	67	0	0
T8	1370	0	0	0
T12	0	2025	0	0
T21	0	74	0	0
T25	0	151	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	248	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	269845322	267540359	0	0
T5	100505	100171	0	0
T6	60041	59974	0	0
T7	4536	4448	0	0
T8	1239	1158	0	0
T26	872	798	0	0
T27	1930	1849	0	0
T28	982	847	0	0
T29	2298	2204	0	0
T30	700	598	0	0
T31	2375	2260	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	32148	0	0
T1	0	112	0	0
T2	0	427	0	0
T3	0	42	0	0
T4	0	48	0	0
T5	56845	34	0	0
T6	20871	24	0	0
T8	1370	0	0	0
T12	0	809	0	0
T21	0	28	0	0
T25	0	52	0	0
T26	1745	0	0	0
T27	977	0	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T33	0	32	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162485875	159864120	0	0
T5	56845	56671	0	0
T6	20871	20851	0	0
T7	2078	2038	0	0
T8	1370	1286	0	0
T26	1745	1596	0	0
T27	977	937	0	0
T28	2047	1764	0	0
T29	1148	1101	0	0
T30	1458	1246	0	0
T31	2474	2354	0	0