Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T5,T26
10CoveredT7,T26,T31
11CoveredT7,T5,T26

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 525732919 5041 0 0
g_div2.Div2Whole_A 525732919 5797 0 0
g_div4.Div4Stepped_A 266651436 4966 0 0
g_div4.Div4Whole_A 266651436 5616 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732919 5041 0 0
T1 0 14 0 0
T2 0 43 0 0
T5 172203 3 0 0
T6 102798 0 0 0
T7 9073 9 0 0
T8 2496 0 0 0
T19 0 6 0 0
T23 0 8 0 0
T24 0 7 0 0
T26 1746 3 0 0
T27 3876 0 0 0
T28 1966 0 0 0
T29 4597 0 0 0
T30 1400 0 0 0
T31 4751 13 0 0
T32 0 14 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732919 5797 0 0
T1 0 15 0 0
T2 0 45 0 0
T5 172203 3 0 0
T6 102798 0 0 0
T7 9073 9 0 0
T8 2496 0 0 0
T19 0 8 0 0
T23 0 8 0 0
T24 0 8 0 0
T26 1746 5 0 0
T27 3876 0 0 0
T28 1966 0 0 0
T29 4597 0 0 0
T30 1400 0 0 0
T31 4751 16 0 0
T32 0 14 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266651436 4966 0 0
T1 0 14 0 0
T2 0 43 0 0
T5 86135 3 0 0
T6 51367 0 0 0
T7 5209 9 0 0
T8 1216 0 0 0
T19 0 6 0 0
T23 0 8 0 0
T24 0 7 0 0
T26 877 3 0 0
T27 1926 0 0 0
T28 916 0 0 0
T29 2246 0 0 0
T30 668 0 0 0
T31 2750 13 0 0
T32 0 14 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266651436 5616 0 0
T1 0 15 0 0
T2 0 45 0 0
T5 86135 3 0 0
T6 51367 0 0 0
T7 5209 9 0 0
T8 1216 0 0 0
T19 0 8 0 0
T23 0 8 0 0
T24 0 8 0 0
T26 877 4 0 0
T27 1926 0 0 0
T28 916 0 0 0
T29 2246 0 0 0
T30 668 0 0 0
T31 2750 16 0 0
T32 0 14 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T5,T26
10CoveredT7,T26,T31
11CoveredT7,T5,T26

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 525732919 5041 0 0
g_div2.Div2Whole_A 525732919 5797 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732919 5041 0 0
T1 0 14 0 0
T2 0 43 0 0
T5 172203 3 0 0
T6 102798 0 0 0
T7 9073 9 0 0
T8 2496 0 0 0
T19 0 6 0 0
T23 0 8 0 0
T24 0 7 0 0
T26 1746 3 0 0
T27 3876 0 0 0
T28 1966 0 0 0
T29 4597 0 0 0
T30 1400 0 0 0
T31 4751 13 0 0
T32 0 14 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 525732919 5797 0 0
T1 0 15 0 0
T2 0 45 0 0
T5 172203 3 0 0
T6 102798 0 0 0
T7 9073 9 0 0
T8 2496 0 0 0
T19 0 8 0 0
T23 0 8 0 0
T24 0 8 0 0
T26 1746 5 0 0
T27 3876 0 0 0
T28 1966 0 0 0
T29 4597 0 0 0
T30 1400 0 0 0
T31 4751 16 0 0
T32 0 14 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T5,T26
10CoveredT7,T26,T31
11CoveredT7,T5,T26

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 266651436 4966 0 0
g_div4.Div4Whole_A 266651436 5616 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266651436 4966 0 0
T1 0 14 0 0
T2 0 43 0 0
T5 86135 3 0 0
T6 51367 0 0 0
T7 5209 9 0 0
T8 1216 0 0 0
T19 0 6 0 0
T23 0 8 0 0
T24 0 7 0 0
T26 877 3 0 0
T27 1926 0 0 0
T28 916 0 0 0
T29 2246 0 0 0
T30 668 0 0 0
T31 2750 13 0 0
T32 0 14 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 266651436 5616 0 0
T1 0 15 0 0
T2 0 45 0 0
T5 86135 3 0 0
T6 51367 0 0 0
T7 5209 9 0 0
T8 1216 0 0 0
T19 0 8 0 0
T23 0 8 0 0
T24 0 8 0 0
T26 877 4 0 0
T27 1926 0 0 0
T28 916 0 0 0
T29 2246 0 0 0
T30 668 0 0 0
T31 2750 16 0 0
T32 0 14 0 0

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