SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T5,T26 |
1 | 0 | Covered | T7,T26,T31 |
1 | 1 | Covered | T7,T5,T26 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 525732919 | 5041 | 0 | 0 |
g_div2.Div2Whole_A | 525732919 | 5797 | 0 | 0 |
g_div4.Div4Stepped_A | 266651436 | 4966 | 0 | 0 |
g_div4.Div4Whole_A | 266651436 | 5616 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 525732919 | 5041 | 0 | 0 |
T1 | 0 | 14 | 0 | 0 |
T2 | 0 | 43 | 0 | 0 |
T5 | 172203 | 3 | 0 | 0 |
T6 | 102798 | 0 | 0 | 0 |
T7 | 9073 | 9 | 0 | 0 |
T8 | 2496 | 0 | 0 | 0 |
T19 | 0 | 6 | 0 | 0 |
T23 | 0 | 8 | 0 | 0 |
T24 | 0 | 7 | 0 | 0 |
T26 | 1746 | 3 | 0 | 0 |
T27 | 3876 | 0 | 0 | 0 |
T28 | 1966 | 0 | 0 | 0 |
T29 | 4597 | 0 | 0 | 0 |
T30 | 1400 | 0 | 0 | 0 |
T31 | 4751 | 13 | 0 | 0 |
T32 | 0 | 14 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 525732919 | 5797 | 0 | 0 |
T1 | 0 | 15 | 0 | 0 |
T2 | 0 | 45 | 0 | 0 |
T5 | 172203 | 3 | 0 | 0 |
T6 | 102798 | 0 | 0 | 0 |
T7 | 9073 | 9 | 0 | 0 |
T8 | 2496 | 0 | 0 | 0 |
T19 | 0 | 8 | 0 | 0 |
T23 | 0 | 8 | 0 | 0 |
T24 | 0 | 8 | 0 | 0 |
T26 | 1746 | 5 | 0 | 0 |
T27 | 3876 | 0 | 0 | 0 |
T28 | 1966 | 0 | 0 | 0 |
T29 | 4597 | 0 | 0 | 0 |
T30 | 1400 | 0 | 0 | 0 |
T31 | 4751 | 16 | 0 | 0 |
T32 | 0 | 14 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 266651436 | 4966 | 0 | 0 |
T1 | 0 | 14 | 0 | 0 |
T2 | 0 | 43 | 0 | 0 |
T5 | 86135 | 3 | 0 | 0 |
T6 | 51367 | 0 | 0 | 0 |
T7 | 5209 | 9 | 0 | 0 |
T8 | 1216 | 0 | 0 | 0 |
T19 | 0 | 6 | 0 | 0 |
T23 | 0 | 8 | 0 | 0 |
T24 | 0 | 7 | 0 | 0 |
T26 | 877 | 3 | 0 | 0 |
T27 | 1926 | 0 | 0 | 0 |
T28 | 916 | 0 | 0 | 0 |
T29 | 2246 | 0 | 0 | 0 |
T30 | 668 | 0 | 0 | 0 |
T31 | 2750 | 13 | 0 | 0 |
T32 | 0 | 14 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 266651436 | 5616 | 0 | 0 |
T1 | 0 | 15 | 0 | 0 |
T2 | 0 | 45 | 0 | 0 |
T5 | 86135 | 3 | 0 | 0 |
T6 | 51367 | 0 | 0 | 0 |
T7 | 5209 | 9 | 0 | 0 |
T8 | 1216 | 0 | 0 | 0 |
T19 | 0 | 8 | 0 | 0 |
T23 | 0 | 8 | 0 | 0 |
T24 | 0 | 8 | 0 | 0 |
T26 | 877 | 4 | 0 | 0 |
T27 | 1926 | 0 | 0 | 0 |
T28 | 916 | 0 | 0 | 0 |
T29 | 2246 | 0 | 0 | 0 |
T30 | 668 | 0 | 0 | 0 |
T31 | 2750 | 16 | 0 | 0 |
T32 | 0 | 14 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T5,T26 |
1 | 0 | Covered | T7,T26,T31 |
1 | 1 | Covered | T7,T5,T26 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 525732919 | 5041 | 0 | 0 |
g_div2.Div2Whole_A | 525732919 | 5797 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 525732919 | 5041 | 0 | 0 |
T1 | 0 | 14 | 0 | 0 |
T2 | 0 | 43 | 0 | 0 |
T5 | 172203 | 3 | 0 | 0 |
T6 | 102798 | 0 | 0 | 0 |
T7 | 9073 | 9 | 0 | 0 |
T8 | 2496 | 0 | 0 | 0 |
T19 | 0 | 6 | 0 | 0 |
T23 | 0 | 8 | 0 | 0 |
T24 | 0 | 7 | 0 | 0 |
T26 | 1746 | 3 | 0 | 0 |
T27 | 3876 | 0 | 0 | 0 |
T28 | 1966 | 0 | 0 | 0 |
T29 | 4597 | 0 | 0 | 0 |
T30 | 1400 | 0 | 0 | 0 |
T31 | 4751 | 13 | 0 | 0 |
T32 | 0 | 14 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 525732919 | 5797 | 0 | 0 |
T1 | 0 | 15 | 0 | 0 |
T2 | 0 | 45 | 0 | 0 |
T5 | 172203 | 3 | 0 | 0 |
T6 | 102798 | 0 | 0 | 0 |
T7 | 9073 | 9 | 0 | 0 |
T8 | 2496 | 0 | 0 | 0 |
T19 | 0 | 8 | 0 | 0 |
T23 | 0 | 8 | 0 | 0 |
T24 | 0 | 8 | 0 | 0 |
T26 | 1746 | 5 | 0 | 0 |
T27 | 3876 | 0 | 0 | 0 |
T28 | 1966 | 0 | 0 | 0 |
T29 | 4597 | 0 | 0 | 0 |
T30 | 1400 | 0 | 0 | 0 |
T31 | 4751 | 16 | 0 | 0 |
T32 | 0 | 14 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T5,T26 |
1 | 0 | Covered | T7,T26,T31 |
1 | 1 | Covered | T7,T5,T26 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 266651436 | 4966 | 0 | 0 |
g_div4.Div4Whole_A | 266651436 | 5616 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 266651436 | 4966 | 0 | 0 |
T1 | 0 | 14 | 0 | 0 |
T2 | 0 | 43 | 0 | 0 |
T5 | 86135 | 3 | 0 | 0 |
T6 | 51367 | 0 | 0 | 0 |
T7 | 5209 | 9 | 0 | 0 |
T8 | 1216 | 0 | 0 | 0 |
T19 | 0 | 6 | 0 | 0 |
T23 | 0 | 8 | 0 | 0 |
T24 | 0 | 7 | 0 | 0 |
T26 | 877 | 3 | 0 | 0 |
T27 | 1926 | 0 | 0 | 0 |
T28 | 916 | 0 | 0 | 0 |
T29 | 2246 | 0 | 0 | 0 |
T30 | 668 | 0 | 0 | 0 |
T31 | 2750 | 13 | 0 | 0 |
T32 | 0 | 14 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 266651436 | 5616 | 0 | 0 |
T1 | 0 | 15 | 0 | 0 |
T2 | 0 | 45 | 0 | 0 |
T5 | 86135 | 3 | 0 | 0 |
T6 | 51367 | 0 | 0 | 0 |
T7 | 5209 | 9 | 0 | 0 |
T8 | 1216 | 0 | 0 | 0 |
T19 | 0 | 8 | 0 | 0 |
T23 | 0 | 8 | 0 | 0 |
T24 | 0 | 8 | 0 | 0 |
T26 | 877 | 4 | 0 | 0 |
T27 | 1926 | 0 | 0 | 0 |
T28 | 916 | 0 | 0 | 0 |
T29 | 2246 | 0 | 0 | 0 |
T30 | 668 | 0 | 0 | 0 |
T31 | 2750 | 16 | 0 | 0 |
T32 | 0 | 14 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |