Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	484837122	413	0	0
StatusRise_A	484837122	413	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484837122	413	0	0
T6	62613	0	0	0
T8	4110	14	0	0
T26	5235	0	0	0
T27	2931	4	0	0
T28	6141	0	0	0
T29	3444	0	0	0
T30	4374	0	0	0
T31	7422	0	0	0
T32	6063	0	0	0
T36	3021	17	0	0
T53	0	10	0	0
T142	0	4	0	0
T159	0	6	0	0
T160	0	8	0	0
T161	0	7	0	0
T162	0	9	0	0
T163	0	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484837122	413	0	0
T6	62613	0	0	0
T8	4110	14	0	0
T26	5235	0	0	0
T27	2931	4	0	0
T28	6141	0	0	0
T29	3444	0	0	0
T30	4374	0	0	0
T31	7422	0	0	0
T32	6063	0	0	0
T36	3021	17	0	0
T53	0	10	0	0
T142	0	4	0	0
T159	0	6	0	0
T160	0	8	0	0
T161	0	7	0	0
T162	0	9	0	0
T163	0	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161612374	140	0	0
StatusRise_A	161612374	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	140	0	0
T6	20871	0	0	0
T8	1370	5	0	0
T26	1745	0	0	0
T27	977	2	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T36	1007	6	0	0
T53	0	3	0	0
T142	0	2	0	0
T159	0	2	0	0
T160	0	4	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	140	0	0
T6	20871	0	0	0
T8	1370	5	0	0
T26	1745	0	0	0
T27	977	2	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T36	1007	6	0	0
T53	0	3	0	0
T142	0	2	0	0
T159	0	2	0	0
T160	0	4	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161612374	134	0	0
StatusRise_A	161612374	134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	134	0	0
T6	20871	0	0	0
T8	1370	4	0	0
T26	1745	0	0	0
T27	977	1	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T36	1007	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	134	0	0
T6	20871	0	0	0
T8	1370	4	0	0
T26	1745	0	0	0
T27	977	1	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T36	1007	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161612374	139	0	0
StatusRise_A	161612374	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	139	0	0
T6	20871	0	0	0
T8	1370	5	0	0
T26	1745	0	0	0
T27	977	1	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T36	1007	4	0	0
T53	0	5	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161612374	139	0	0
T6	20871	0	0	0
T8	1370	5	0	0
T26	1745	0	0	0
T27	977	1	0	0
T28	2047	0	0	0
T29	1148	0	0	0
T30	1458	0	0	0
T31	2474	0	0	0
T32	2021	0	0	0
T36	1007	4	0	0
T53	0	5	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	3	0	0