Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50019	0	0
CgEnOn_A	2147483647	41164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50019	0	0
T1	0	13	0	0
T2	0	30	0	0
T5	1215442	63	0	0
T6	1389640	3	0	0
T7	21419	3	0	0
T8	26780	40	0	0
T20	0	1	0	0
T26	19636	3	0	0
T27	43166	13	0	0
T28	21842	3	0	0
T29	51506	3	0	0
T30	15618	28	0	0
T31	54940	3	0	0
T32	180352	0	0	0
T36	16266	41	0	0
T53	0	10	0	0
T142	0	5	0	0
T159	0	12	0	0
T160	0	10	0	0
T161	0	15	0	0
T162	0	15	0	0
T163	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41164	0	0
T1	0	169	0	0
T2	0	293	0	0
T5	1215442	75	0	0
T6	1389640	0	0	0
T8	26780	72	0	0
T20	0	8	0	0
T21	0	23	0	0
T26	19636	0	0	0
T27	43166	22	0	0
T28	21842	0	0	0
T29	51506	0	0	0
T30	15618	35	0	0
T31	54940	0	0	0
T32	227412	0	0	0
T33	0	4	0	0
T36	16266	100	0	0
T53	0	21	0	0
T109	0	34	0	0
T142	0	10	0	0
T159	0	32	0	0
T160	0	20	0	0
T161	0	21	0	0
T162	0	24	0	0
T163	0	31	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	266651037	139	0	0
CgEnOn_A	266651037	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266651037	139	0	0
T6	51366	0	0	0
T8	1215	4	0	0
T26	876	0	0	0
T27	1926	1	0	0
T28	916	0	0	0
T29	2245	0	0	0
T30	667	0	0	0
T31	2750	0	0	0
T32	11962	0	0	0
T36	1705	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266651037	139	0	0
T6	51366	0	0	0
T8	1215	4	0	0
T26	876	0	0	0
T27	1926	1	0	0
T28	916	0	0	0
T29	2245	0	0	0
T30	667	0	0	0
T31	2750	0	0	0
T32	11962	0	0	0
T36	1705	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133324836	139	0	0
CgEnOn_A	133324836	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133324836	139	0	0
T6	25683	0	0	0
T8	608	4	0	0
T26	437	0	0	0
T27	963	1	0	0
T28	458	0	0	0
T29	1123	0	0	0
T30	334	0	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	852	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133324836	139	0	0
T6	25683	0	0	0
T8	608	4	0	0
T26	437	0	0	0
T27	963	1	0	0
T28	458	0	0	0
T29	1123	0	0	0
T30	334	0	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	852	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133324836	139	0	0
CgEnOn_A	133324836	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133324836	139	0	0
T6	25683	0	0	0
T8	608	4	0	0
T26	437	0	0	0
T27	963	1	0	0
T28	458	0	0	0
T29	1123	0	0	0
T30	334	0	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	852	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133324836	139	0	0
T6	25683	0	0	0
T8	608	4	0	0
T26	437	0	0	0
T27	963	1	0	0
T28	458	0	0	0
T29	1123	0	0	0
T30	334	0	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	852	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133324836	139	0	0
CgEnOn_A	133324836	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133324836	139	0	0
T6	25683	0	0	0
T8	608	4	0	0
T26	437	0	0	0
T27	963	1	0	0
T28	458	0	0	0
T29	1123	0	0	0
T30	334	0	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	852	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133324836	139	0	0
T6	25683	0	0	0
T8	608	4	0	0
T26	437	0	0	0
T27	963	1	0	0
T28	458	0	0	0
T29	1123	0	0	0
T30	334	0	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	852	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	525732438	139	0	0
CgEnOn_A	525732438	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525732438	139	0	0
T6	102798	0	0	0
T8	2496	4	0	0
T26	1745	0	0	0
T27	3876	1	0	0
T28	1966	0	0	0
T29	4597	0	0	0
T30	1400	0	0	0
T31	4750	0	0	0
T32	19412	0	0	0
T36	3461	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525732438	134	0	0
T6	102798	0	0	0
T8	2496	4	0	0
T26	1745	0	0	0
T27	3876	1	0	0
T28	1966	0	0	0
T29	4597	0	0	0
T30	1400	0	0	0
T31	4750	0	0	0
T32	19412	0	0	0
T36	3461	7	0	0
T53	0	2	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	559488063	144	0	0
CgEnOn_A	559488063	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	144	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T18	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T36	3451	6	0	0
T53	0	3	0	0
T142	0	2	0	0
T159	0	2	0	0
T160	0	4	0	0
T161	0	2	0	0
T162	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	141	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T36	3451	6	0	0
T53	0	3	0	0
T142	0	2	0	0
T159	0	2	0	0
T160	0	4	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	559488063	144	0	0
CgEnOn_A	559488063	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	144	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T18	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T36	3451	6	0	0
T53	0	3	0	0
T142	0	2	0	0
T159	0	2	0	0
T160	0	4	0	0
T161	0	2	0	0
T162	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	141	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T36	3451	6	0	0
T53	0	3	0	0
T142	0	2	0	0
T159	0	2	0	0
T160	0	4	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Unreachable
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	268616400	141	0	0
CgEnOn_A	268616400	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268616400	141	0	0
T2	0	1	0	0
T6	60041	0	0	0
T8	1239	5	0	0
T26	872	0	0	0
T27	1930	1	0	0
T28	982	0	0	0
T29	2298	0	0	0
T30	700	0	0	0
T31	2375	0	0	0
T32	9706	0	0	0
T36	1642	4	0	0
T53	0	5	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0
T162	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268616400	139	0	0
T6	60041	0	0	0
T8	1239	5	0	0
T26	872	0	0	0
T27	1930	1	0	0
T28	982	0	0	0
T29	2298	0	0	0
T30	700	0	0	0
T31	2375	0	0	0
T32	9706	0	0	0
T36	1642	4	0	0
T53	0	5	0	0
T142	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T36
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133324836	7936	0	0
CgEnOn_A	133324836	5731	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133324836	7936	0	0
T5	43067	21	0	0
T6	25683	1	0	0
T7	2602	1	0	0
T8	608	5	0	0
T26	437	1	0	0
T27	963	2	0	0
T28	458	1	0	0
T29	1123	1	0	0
T30	334	8	0	0
T31	1374	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133324836	5731	0	0
T1	0	32	0	0
T2	0	42	0	0
T5	43067	18	0	0
T6	25683	0	0	0
T8	608	4	0	0
T20	0	1	0	0
T21	0	5	0	0
T26	437	0	0	0
T27	963	1	0	0
T28	458	0	0	0
T29	1123	0	0	0
T30	334	7	0	0
T31	1374	0	0	0
T32	5980	0	0	0
T36	0	7	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T36
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	266651037	8031	0	0
CgEnOn_A	266651037	5826	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266651037	8031	0	0
T5	86135	21	0	0
T6	51366	1	0	0
T7	5208	1	0	0
T8	1215	5	0	0
T26	876	1	0	0
T27	1926	2	0	0
T28	916	1	0	0
T29	2245	1	0	0
T30	667	10	0	0
T31	2750	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266651037	5826	0	0
T1	0	29	0	0
T2	0	40	0	0
T5	86135	18	0	0
T6	51366	0	0	0
T8	1215	4	0	0
T20	0	1	0	0
T21	0	6	0	0
T26	876	0	0	0
T27	1926	1	0	0
T28	916	0	0	0
T29	2245	0	0	0
T30	667	9	0	0
T31	2750	0	0	0
T32	11962	0	0	0
T36	0	7	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T36
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	525732438	8019	0	0
CgEnOn_A	525732438	5809	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525732438	8019	0	0
T5	172203	20	0	0
T6	102798	1	0	0
T7	9073	1	0	0
T8	2496	5	0	0
T26	1745	1	0	0
T27	3876	2	0	0
T28	1966	1	0	0
T29	4597	1	0	0
T30	1400	10	0	0
T31	4750	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525732438	5809	0	0
T1	0	30	0	0
T2	0	43	0	0
T5	172203	17	0	0
T6	102798	0	0	0
T8	2496	4	0	0
T20	0	1	0	0
T21	0	6	0	0
T26	1745	0	0	0
T27	3876	1	0	0
T28	1966	0	0	0
T29	4597	0	0	0
T30	1400	9	0	0
T31	4750	0	0	0
T32	19412	0	0	0
T36	0	7	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T36
1	0	Covered	T7,T5,T8
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	268616400	8048	0	0
CgEnOn_A	268616400	5838	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268616400	8048	0	0
T5	100505	21	0	0
T6	60041	1	0	0
T7	4536	1	0	0
T8	1239	6	0	0
T26	872	1	0	0
T27	1930	2	0	0
T28	982	1	0	0
T29	2298	1	0	0
T30	700	11	0	0
T31	2375	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268616400	5838	0	0
T1	0	31	0	0
T2	0	48	0	0
T5	100505	18	0	0
T6	60041	0	0	0
T8	1239	5	0	0
T20	0	1	0	0
T21	0	6	0	0
T26	872	0	0	0
T27	1930	1	0	0
T28	982	0	0	0
T29	2298	0	0	0
T30	700	10	0	0
T31	2375	0	0	0
T32	9706	0	0	0
T36	0	4	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Covered	T5,T1,T20
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	559488063	4189	0	0
CgEnOn_A	559488063	4186	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	4189	0	0
T1	0	13	0	0
T2	0	30	0	0
T5	203383	1	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T20	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T36	0	6	0	0
T109	0	10	0	0
T159	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	4186	0	0
T1	0	13	0	0
T2	0	30	0	0
T5	203383	1	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T20	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T36	0	6	0	0
T109	0	10	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Covered	T5,T1,T20
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	559488063	4224	0	0
CgEnOn_A	559488063	4221	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	4224	0	0
T1	0	12	0	0
T2	0	35	0	0
T5	203383	1	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T20	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T36	0	6	0	0
T109	0	8	0	0
T159	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	4221	0	0
T1	0	12	0	0
T2	0	35	0	0
T5	203383	1	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T20	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T36	0	6	0	0
T109	0	8	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Covered	T5,T1,T20
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	559488063	4214	0	0
CgEnOn_A	559488063	4211	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	4214	0	0
T1	0	11	0	0
T2	0	28	0	0
T5	203383	1	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T20	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T36	0	6	0	0
T109	0	6	0	0
T159	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	4211	0	0
T1	0	11	0	0
T2	0	28	0	0
T5	203383	1	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T20	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T36	0	6	0	0
T109	0	6	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T27
1	0	Covered	T5,T1,T20
1	1	Covered	T7,T5,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	559488063	4234	0	0
CgEnOn_A	559488063	4231	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	4234	0	0
T1	0	11	0	0
T2	0	27	0	0
T5	203383	1	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T20	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T36	0	6	0	0
T109	0	10	0	0
T159	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	559488063	4231	0	0
T1	0	11	0	0
T2	0	27	0	0
T5	203383	1	0	0
T6	143083	0	0	0
T8	2408	5	0	0
T20	0	1	0	0
T26	1817	0	0	0
T27	3975	2	0	0
T28	2047	0	0	0
T29	4789	0	0	0
T30	1458	0	0	0
T31	4949	0	0	0
T32	20222	0	0	0
T33	0	1	0	0
T36	0	6	0	0
T109	0	10	0	0
T159	0	2	0	0