Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	654786	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3685267

1

T8

5

T9

18

T10

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1059281	1			T9	19		T10	20		T28	5
values[0x0]	1511270	1			T8	14		T9	19		T10	25
values[0x1]	1769502	1			T8	15		T9	20		T10	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	364942	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3975111

1

T8

7

T9

24

T10

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15934	1			T5	2		T40	2		T1	596
valid_sources[0x01]	16531	1			T1	583		T20	2		T3	1
valid_sources[0x02]	15772	1			T1	568		T20	3		T3	1
valid_sources[0x03]	16056	1			T5	3		T40	3		T1	607
valid_sources[0x04]	18542	1			T5	2		T31	1		T1	603
valid_sources[0x05]	17231	1			T5	1		T40	1		T1	616
valid_sources[0x06]	17696	1			T29	1		T1	605		T20	2
valid_sources[0x07]	16813	1			T7	1		T40	1		T1	563
valid_sources[0x08]	16978	1			T8	1		T5	1		T37	54
valid_sources[0x09]	17757	1			T5	3		T1	578		T146	1
valid_sources[0x0a]	17445	1			T5	3		T1	600		T20	6
valid_sources[0x0b]	16616	1			T5	1		T7	1		T1	651
valid_sources[0x0c]	17345	1			T1	570		T2	3		T20	2
valid_sources[0x0d]	16420	1			T8	1		T1	544		T20	6
valid_sources[0x0e]	16765	1			T1	558		T2	1		T20	2
valid_sources[0x0f]	17057	1			T5	1		T31	1		T1	622
valid_sources[0x10]	16096	1			T31	1		T40	1		T1	446
valid_sources[0x11]	18072	1			T5	1		T47	1		T1	619
valid_sources[0x12]	16230	1			T5	1		T1	555		T20	3
valid_sources[0x13]	17027	1			T29	1		T5	3		T1	587
valid_sources[0x14]	17902	1			T5	1		T40	1		T1	566
valid_sources[0x15]	16800	1			T8	1		T29	1		T40	2
valid_sources[0x16]	18407	1			T5	1		T47	1		T1	568
valid_sources[0x17]	17893	1			T5	1		T1	624		T20	3
valid_sources[0x18]	17425	1			T5	2		T36	61		T1	568
valid_sources[0x19]	16412	1			T8	1		T5	4		T1	631
valid_sources[0x1a]	16557	1			T1	517		T20	1		T14	122
valid_sources[0x1b]	17004	1			T7	1		T1	621		T20	7
valid_sources[0x1c]	16463	1			T5	1		T40	2		T1	604
valid_sources[0x1d]	18897	1			T40	3		T1	573		T2	2
valid_sources[0x1e]	16958	1			T5	2		T40	2		T1	632
valid_sources[0x1f]	15575	1			T5	5		T40	2		T4	28
valid_sources[0x20]	17350	1			T5	3		T1	544		T20	3
valid_sources[0x21]	19337	1			T5	5		T40	3		T1	540
valid_sources[0x22]	18297	1			T1	570		T20	2		T3	1
valid_sources[0x23]	16454	1			T1	619		T14	111		T77	5
valid_sources[0x24]	16820	1			T5	2		T1	566		T3	1
valid_sources[0x25]	17297	1			T5	1		T40	2		T1	624
valid_sources[0x26]	19532	1			T8	2		T5	1		T1	568
valid_sources[0x27]	18895	1			T5	2		T1	613		T2	1
valid_sources[0x28]	17868	1			T5	2		T1	679		T2	1
valid_sources[0x29]	17592	1			T5	4		T40	2		T4	15
valid_sources[0x2a]	17120	1			T5	3		T31	1		T1	583
valid_sources[0x2b]	19346	1			T5	5		T1	569		T20	1
valid_sources[0x2c]	16359	1			T8	2		T5	3		T1	536
valid_sources[0x2d]	17276	1			T5	1		T1	598		T20	6
valid_sources[0x2e]	17673	1			T5	3		T1	577		T20	3
valid_sources[0x2f]	16373	1			T7	1		T1	598		T20	3
valid_sources[0x30]	15928	1			T40	2		T1	566		T20	4
valid_sources[0x31]	16366	1			T5	3		T31	1		T1	565
valid_sources[0x32]	17337	1			T28	16		T5	4		T1	540
valid_sources[0x33]	16366	1			T5	3		T40	4		T1	547
valid_sources[0x34]	15839	1			T40	2		T1	559		T2	1
valid_sources[0x35]	16724	1			T8	1		T5	1		T1	612
valid_sources[0x36]	16402	1			T5	1		T4	23		T1	653
valid_sources[0x37]	14764	1			T5	1		T40	1		T1	571
valid_sources[0x38]	15872	1			T5	2		T40	1		T1	583
valid_sources[0x39]	17015	1			T5	3		T1	534		T2	1
valid_sources[0x3a]	16958	1			T1	651		T20	1		T146	1
valid_sources[0x3b]	18344	1			T29	1		T5	1		T1	602
valid_sources[0x3c]	17171	1			T5	2		T31	1		T40	1
valid_sources[0x3d]	17585	1			T5	4		T1	624		T2	1
valid_sources[0x3e]	16209	1			T5	3		T40	1		T1	535
valid_sources[0x3f]	16812	1			T40	2		T1	549		T2	1
valid_sources[0x40]	16684	1			T5	1		T1	599		T20	6
valid_sources[0x41]	16296	1			T1	534		T20	2		T24	1
valid_sources[0x42]	17811	1			T5	1		T1	642		T20	2
valid_sources[0x43]	16235	1			T40	3		T1	580		T20	2
valid_sources[0x44]	17141	1			T5	1		T40	1		T1	581
valid_sources[0x45]	17315	1			T5	4		T40	1		T1	603
valid_sources[0x46]	16570	1			T29	1		T5	3		T1	519
valid_sources[0x47]	17332	1			T5	1		T1	506		T20	4
valid_sources[0x48]	16148	1			T8	1		T29	1		T5	1
valid_sources[0x49]	17377	1			T5	4		T40	1		T1	493
valid_sources[0x4a]	18680	1			T5	1		T1	543		T20	5
valid_sources[0x4b]	15737	1			T5	2		T1	583		T2	1
valid_sources[0x4c]	17669	1			T5	3		T40	2		T4	46
valid_sources[0x4d]	17034	1			T29	1		T7	1		T40	1
valid_sources[0x4e]	16995	1			T5	3		T7	1		T40	1
valid_sources[0x4f]	15178	1			T29	1		T5	1		T31	1
valid_sources[0x50]	17827	1			T5	1		T1	629		T2	3
valid_sources[0x51]	17223	1			T8	1		T30	15		T5	1
valid_sources[0x52]	16954	1			T1	583		T20	5		T3	1
valid_sources[0x53]	16908	1			T5	2		T4	90		T1	621
valid_sources[0x54]	16650	1			T5	1		T1	542		T20	3
valid_sources[0x55]	17477	1			T5	1		T1	577		T20	1
valid_sources[0x56]	17009	1			T5	2		T40	2		T1	648
valid_sources[0x57]	16318	1			T5	1		T1	504		T20	1
valid_sources[0x58]	16993	1			T5	4		T1	507		T20	7
valid_sources[0x59]	16090	1			T5	1		T1	538		T2	1
valid_sources[0x5a]	16529	1			T8	1		T40	1		T1	624
valid_sources[0x5b]	17452	1			T5	2		T1	539		T20	3
valid_sources[0x5c]	17933	1			T5	1		T40	1		T1	592
valid_sources[0x5d]	18514	1			T5	3		T7	1		T40	1
valid_sources[0x5e]	15799	1			T5	2		T7	1		T40	1
valid_sources[0x5f]	16095	1			T5	2		T4	213		T1	585
valid_sources[0x60]	18316	1			T5	3		T1	595		T20	2
valid_sources[0x61]	16866	1			T5	1		T40	2		T1	561
valid_sources[0x62]	16496	1			T29	2		T5	4		T40	2
valid_sources[0x63]	17329	1			T5	3		T1	627		T20	3
valid_sources[0x64]	16065	1			T1	519		T20	3		T14	129
valid_sources[0x65]	16262	1			T5	1		T1	504		T20	5
valid_sources[0x66]	16323	1			T1	517		T20	5		T3	2
valid_sources[0x67]	15606	1			T5	1		T31	1		T1	523
valid_sources[0x68]	16973	1			T31	1		T1	596		T20	4
valid_sources[0x69]	17129	1			T8	1		T1	555		T20	2
valid_sources[0x6a]	15037	1			T1	542		T2	1		T20	1
valid_sources[0x6b]	16302	1			T8	1		T47	1		T1	569
valid_sources[0x6c]	17143	1			T8	1		T5	1		T1	581
valid_sources[0x6d]	17274	1			T9	58		T5	2		T1	616
valid_sources[0x6e]	16016	1			T29	1		T5	1		T31	1
valid_sources[0x6f]	16924	1			T29	4		T7	2		T1	645
valid_sources[0x70]	16443	1			T31	1		T1	534		T2	4
valid_sources[0x71]	17352	1			T5	1		T40	4		T1	607
valid_sources[0x72]	16120	1			T5	1		T1	547		T20	3
valid_sources[0x73]	17740	1			T5	1		T40	1		T1	672
valid_sources[0x74]	17587	1			T4	55		T1	582		T20	3
valid_sources[0x75]	17059	1			T5	2		T40	1		T1	641
valid_sources[0x76]	17950	1			T5	3		T40	2		T47	1
valid_sources[0x77]	16689	1			T5	1		T4	34		T1	518
valid_sources[0x78]	16633	1			T5	1		T1	566		T20	6
valid_sources[0x79]	18454	1			T5	1		T38	4		T1	576
valid_sources[0x7a]	15895	1			T5	1		T1	622		T20	6
valid_sources[0x7b]	16206	1			T1	642		T2	1		T20	7
valid_sources[0x7c]	16867	1			T5	3		T7	1		T4	6
valid_sources[0x7d]	16487	1			T5	2		T31	1		T1	530
valid_sources[0x7e]	17706	1			T29	1		T5	3		T1	598
valid_sources[0x7f]	17031	1			T5	1		T40	1		T1	602
valid_sources[0x80]	16360	1			T1	580		T20	3		T111	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

927113

1

T9

8

T10

10

T28

1

values[0x0]

all_enables

biggest_size

1406821

1

T8

4

T9

6

T10

5

values[0x1]

all_enables

biggest_size

1351333

1

T8

1

T9

4

T10

2