Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
1	0	Covered	T8,T9,T10

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T29,T30
1	0	Covered	T32,T48,T49
1	1	Covered	T8,T9,T10

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1105822219	15989	0	0
GateOpen_A	1105822219	22332	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1105822219	15989	0	0
T1	0	511	0	0
T5	405423	0	0	0
T6	139300	0	0	0
T8	4004	29	0	0
T9	19899	0	0	0
T10	7727	0	0	0
T14	0	124	0	0
T21	0	42	0	0
T24	0	4	0	0
T27	0	31	0	0
T28	38756	0	0	0
T29	2931	21	0	0
T30	7968	9	0	0
T31	11283	0	0	0
T32	7328	10	0	0
T48	0	13	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1105822219	22332	0	0
T1	0	535	0	0
T2	0	4	0	0
T4	0	56	0	0
T5	405423	0	0	0
T6	139300	0	0	0
T8	4004	29	0	0
T9	19899	4	0	0
T10	7727	4	0	0
T28	38756	4	0	0
T29	2931	25	0	0
T30	7968	13	0	0
T31	11283	0	0	0
T32	7328	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
1	0	Covered	T8,T9,T10

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T29,T30
1	0	Covered	T32,T48,T49
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	121926061	3848	0	0
GateOpen_A	121926061	5431	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121926061	3848	0	0
T1	0	124	0	0
T5	45031	0	0	0
T6	15467	0	0	0
T8	432	5	0	0
T9	2483	0	0	0
T10	904	0	0	0
T14	0	28	0	0
T21	0	12	0	0
T24	0	1	0	0
T27	0	8	0	0
T28	4307	0	0	0
T29	322	5	0	0
T30	917	2	0	0
T31	1284	0	0	0
T32	818	2	0	0
T48	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121926061	5431	0	0
T1	0	130	0	0
T2	0	1	0	0
T4	0	14	0	0
T5	45031	0	0	0
T6	15467	0	0	0
T8	432	5	0	0
T9	2483	1	0	0
T10	904	1	0	0
T28	4307	1	0	0
T29	322	6	0	0
T30	917	3	0	0
T31	1284	0	0	0
T32	818	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
1	0	Covered	T8,T9,T10

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T29,T30
1	0	Covered	T32,T48,T49
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	243853041	4061	0	0
GateOpen_A	243853041	5644	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243853041	4061	0	0
T1	0	133	0	0
T5	90062	0	0	0
T6	30933	0	0	0
T8	864	8	0	0
T9	4970	0	0	0
T10	1811	0	0	0
T14	0	33	0	0
T21	0	11	0	0
T24	0	1	0	0
T27	0	7	0	0
T28	8613	0	0	0
T29	643	6	0	0
T30	1837	3	0	0
T31	2569	0	0	0
T32	1636	2	0	0
T48	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243853041	5644	0	0
T1	0	139	0	0
T2	0	1	0	0
T4	0	14	0	0
T5	90062	0	0	0
T6	30933	0	0	0
T8	864	8	0	0
T9	4970	1	0	0
T10	1811	1	0	0
T28	8613	1	0	0
T29	643	7	0	0
T30	1837	4	0	0
T31	2569	0	0	0
T32	1636	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
1	0	Covered	T8,T9,T10

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T29,T30
1	0	Covered	T32,T48,T49
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	489171663	4052	0	0
GateOpen_A	489171663	5640	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489171663	4052	0	0
T1	0	127	0	0
T5	180217	0	0	0
T6	61932	0	0	0
T8	1805	6	0	0
T9	8297	0	0	0
T10	3341	0	0	0
T14	0	30	0	0
T21	0	9	0	0
T24	0	1	0	0
T27	0	8	0	0
T28	17224	0	0	0
T29	1311	5	0	0
T30	3476	2	0	0
T31	4953	0	0	0
T32	3309	2	0	0
T48	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489171663	5640	0	0
T1	0	133	0	0
T2	0	1	0	0
T4	0	14	0	0
T5	180217	0	0	0
T6	61932	0	0	0
T8	1805	6	0	0
T9	8297	1	0	0
T10	3341	1	0	0
T28	17224	1	0	0
T29	1311	6	0	0
T30	3476	3	0	0
T31	4953	0	0	0
T32	3309	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
1	0	Covered	T8,T9,T10

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T29,T30
1	0	Covered	T32,T48,T49
1	1	Covered	T8,T9,T10

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	250871454	4028	0	0
GateOpen_A	250871454	5617	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250871454	4028	0	0
T1	0	127	0	0
T5	90113	0	0	0
T6	30968	0	0	0
T8	903	10	0	0
T9	4149	0	0	0
T10	1671	0	0	0
T14	0	33	0	0
T21	0	10	0	0
T24	0	1	0	0
T27	0	8	0	0
T28	8612	0	0	0
T29	655	5	0	0
T30	1738	2	0	0
T31	2477	0	0	0
T32	1565	4	0	0
T48	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	250871454	5617	0	0
T1	0	133	0	0
T2	0	1	0	0
T4	0	14	0	0
T5	90113	0	0	0
T6	30968	0	0	0
T8	903	10	0	0
T9	4149	1	0	0
T10	1671	1	0	0
T28	8612	1	0	0
T29	655	6	0	0
T30	1738	3	0	0
T31	2477	0	0	0
T32	1565	5	0	0