Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	841385305	80271	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841385305	80271	0	0
T1	2031245	1105	0	0
T2	261785	83	0	0
T3	0	310	0	0
T13	0	476	0	0
T14	0	257	0	0
T15	0	216	0	0
T16	0	321	0	0
T17	0	287	0	0
T18	0	1423	0	0
T19	0	578	0	0
T20	635235	0	0	0
T21	6585	0	0	0
T22	4440	0	0	0
T23	12275	0	0	0
T24	11465	0	0	0
T25	318045	0	0	0
T26	7510	0	0	0
T27	314330	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168277061	11981	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	11981	0	0
T1	406249	178	0	0
T2	52357	11	0	0
T3	0	42	0	0
T13	0	70	0	0
T14	0	37	0	0
T15	0	34	0	0
T16	0	59	0	0
T17	0	36	0	0
T18	0	284	0	0
T19	0	97	0	0
T20	127047	0	0	0
T21	1317	0	0	0
T22	888	0	0	0
T23	2455	0	0	0
T24	2293	0	0	0
T25	63609	0	0	0
T26	1502	0	0	0
T27	62866	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168277061	11783	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	11783	0	0
T1	406249	172	0	0
T2	52357	10	0	0
T3	0	40	0	0
T13	0	68	0	0
T14	0	36	0	0
T15	0	34	0	0
T16	0	59	0	0
T17	0	42	0	0
T18	0	284	0	0
T19	0	97	0	0
T20	127047	0	0	0
T21	1317	0	0	0
T22	888	0	0	0
T23	2455	0	0	0
T24	2293	0	0	0
T25	63609	0	0	0
T26	1502	0	0	0
T27	62866	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168277061	16234	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	16234	0	0
T1	406249	223	0	0
T2	52357	17	0	0
T3	0	63	0	0
T13	0	95	0	0
T14	0	58	0	0
T15	0	44	0	0
T16	0	62	0	0
T17	0	57	0	0
T18	0	284	0	0
T19	0	117	0	0
T20	127047	0	0	0
T21	1317	0	0	0
T22	888	0	0	0
T23	2455	0	0	0
T24	2293	0	0	0
T25	63609	0	0	0
T26	1502	0	0	0
T27	62866	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168277061	16128	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	16128	0	0
T1	406249	225	0	0
T2	52357	17	0	0
T3	0	65	0	0
T13	0	97	0	0
T14	0	50	0	0
T15	0	44	0	0
T16	0	62	0	0
T17	0	57	0	0
T18	0	284	0	0
T19	0	117	0	0
T20	127047	0	0	0
T21	1317	0	0	0
T22	888	0	0	0
T23	2455	0	0	0
T24	2293	0	0	0
T25	63609	0	0	0
T26	1502	0	0	0
T27	62866	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168277061	24145	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	24145	0	0
T1	406249	307	0	0
T2	52357	28	0	0
T3	0	100	0	0
T13	0	146	0	0
T14	0	76	0	0
T15	0	60	0	0
T16	0	79	0	0
T17	0	95	0	0
T18	0	287	0	0
T19	0	150	0	0
T20	127047	0	0	0
T21	1317	0	0	0
T22	888	0	0	0
T23	2455	0	0	0
T24	2293	0	0	0
T25	63609	0	0	0
T26	1502	0	0	0
T27	62866	0	0	0