Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_io_step_down_req_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_step_down_req_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_io_div4_div_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_main_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div2_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_io_div4_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_usb_root_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_io_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf 100.00 100.00
gen_flops.gen_stable_chks.u_mubi_xor 100.00 100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage 100.00 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_step_down_req_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync

Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_div2_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_div_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_io_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_usb_peri_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_io_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_main_meas.u_calib_rdy_sync

SCORELINE
100.00 100.00
tb.dut.u_usb_meas.u_calib_rdy_sync

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Cond Coverage for Module : prim_mubi4_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

Branch Coverage for Module : prim_mubi4_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 22540 22540 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 1009662366 996567618 0 14490
gen_flops.gen_stable_chks.OutputDelay_A 2147483647 2147483647 0 16905
gen_flops.gen_stable_chks.OutputIfUnstable_A 2147483647 205251 0 0
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 22540 22540 0 0
T5 28 28 0 0
T6 28 28 0 0
T8 28 28 0 0
T9 28 28 0 0
T10 28 28 0 0
T28 28 28 0 0
T29 28 28 0 0
T30 28 28 0 0
T31 28 28 0 0
T32 28 28 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T5 4824697 4820019 0 0
T6 926348 924618 0 0
T8 48804 44098 0 0
T9 138659 136226 0 0
T10 68668 67210 0 0
T28 232521 230317 0 0
T29 35256 32979 0 0
T30 94702 88954 0 0
T31 80710 77841 0 0
T32 53294 51995 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1009662366 996567618 0 14490
T5 1092630 1091466 0 18
T6 61926 61776 0 18
T8 11172 9984 0 18
T9 14004 13710 0 18
T10 11268 10986 0 18
T28 6456 6366 0 18
T29 8028 7434 0 18
T30 21720 20262 0 18
T31 7734 7398 0 18
T32 5226 5070 0 18

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 16905
T5 1295355 1293974 0 21
T6 340629 339870 0 21
T8 13053 11661 0 21
T9 47537 46585 0 21
T10 21012 20491 0 21
T28 91144 90122 0 21
T29 9446 8751 0 21
T30 25196 23504 0 21
T31 28166 26992 0 21
T32 18591 18038 0 21

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 205251 0 0
T1 0 858 0 0
T5 1295355 4 0 0
T6 340629 4 0 0
T8 7524 56 0 0
T9 47537 212 0 0
T10 21012 183 0 0
T22 0 1 0 0
T23 0 86 0 0
T26 0 11 0 0
T27 0 64 0 0
T28 91144 53 0 0
T29 9446 44 0 0
T30 25196 222 0 0
T31 28166 97 0 0
T32 18591 48 0 0
T36 8019 204 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T5 2436712 2434540 0 0
T6 523793 522933 0 0
T8 24579 22414 0 0
T9 77118 75892 0 0
T10 36388 35694 0 0
T28 134921 133790 0 0
T29 17782 16755 0 0
T30 47786 45149 0 0
T31 44810 43412 0 0
T32 29477 28848 0 0

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 489171267 485133746 0 0
gen_flops.gen_stable_chks.OutputDelay_A 489171267 485126900 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 489171267 28120 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171267 485133746 0 0
T5 180217 180027 0 0
T6 61931 61797 0 0
T8 1805 1616 0 0
T9 8297 8134 0 0
T10 3340 3260 0 0
T28 17224 17035 0 0
T29 1310 1216 0 0
T30 3476 3245 0 0
T31 4952 4749 0 0
T32 3309 3215 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171267 485126900 0 2415
T5 180217 180024 0 3
T6 61931 61794 0 3
T8 1805 1613 0 3
T9 8297 8131 0 3
T10 3340 3257 0 3
T28 17224 17032 0 3
T29 1310 1213 0 3
T30 3476 3242 0 3
T31 4952 4746 0 3
T32 3309 3212 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171267 28120 0 0
T1 0 349 0 0
T5 180217 0 0 0
T6 61931 0 0 0
T9 8297 57 0 0
T10 3340 50 0 0
T23 0 44 0 0
T26 0 6 0 0
T27 0 39 0 0
T28 17224 14 0 0
T29 1310 0 0 0
T30 3476 51 0 0
T31 4952 27 0 0
T32 3309 0 0 0
T36 2673 104 0 0

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_no_flops.OutputDelay_A 168277061 166101610 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_no_flops.OutputDelay_A 168277061 166101610 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_flops.gen_stable_chks.OutputDelay_A 168277061 166094603 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 168277061 17391 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166094603 0 2415
T5 182105 181911 0 3
T6 10321 10296 0 3
T8 1862 1664 0 3
T9 2334 2285 0 3
T10 1878 1831 0 3
T28 1076 1061 0 3
T29 1338 1239 0 3
T30 3620 3377 0 3
T31 1289 1233 0 3
T32 871 845 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 17391 0 0
T1 0 235 0 0
T5 182105 0 0 0
T6 10321 0 0 0
T9 2334 40 0 0
T10 1878 10 0 0
T23 0 4 0 0
T26 0 3 0 0
T27 0 25 0 0
T28 1076 10 0 0
T29 1338 0 0 0
T30 3620 37 0 0
T31 1289 20 0 0
T32 871 0 0 0
T36 2673 53 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT9,T10,T28

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T28
0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_flops.gen_stable_chks.OutputDelay_A 168277061 166094603 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 168277061 20304 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166094603 0 2415
T5 182105 181911 0 3
T6 10321 10296 0 3
T8 1862 1664 0 3
T9 2334 2285 0 3
T10 1878 1831 0 3
T28 1076 1061 0 3
T29 1338 1239 0 3
T30 3620 3377 0 3
T31 1289 1233 0 3
T32 871 845 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 20304 0 0
T1 0 274 0 0
T5 182105 0 0 0
T6 10321 0 0 0
T9 2334 41 0 0
T10 1878 45 0 0
T22 0 1 0 0
T23 0 38 0 0
T26 0 2 0 0
T28 1076 7 0 0
T29 1338 0 0 0
T30 3620 32 0 0
T31 1289 8 0 0
T32 871 0 0 0
T36 2673 47 0 0

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 520398119 0 0
gen_no_flops.OutputDelay_A 522561045 520398119 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 520398119 0 0
T5 187732 187635 0 0
T6 64514 64445 0 0
T8 1881 1797 0 0
T9 8643 8531 0 0
T10 3479 3439 0 0
T28 17942 17831 0 0
T29 1365 1339 0 0
T30 3620 3523 0 0
T31 5159 5062 0 0
T32 3385 3344 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 520398119 0 0
T5 187732 187635 0 0
T6 64514 64445 0 0
T8 1881 1797 0 0
T9 8643 8531 0 0
T10 3479 3439 0 0
T28 17942 17831 0 0
T29 1365 1339 0 0
T30 3620 3523 0 0
T31 5159 5062 0 0
T32 3385 3344 0 0

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 489171267 487131151 0 0
gen_no_flops.OutputDelay_A 489171267 487131151 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171267 487131151 0 0
T5 180217 180123 0 0
T6 61931 61865 0 0
T8 1805 1726 0 0
T9 8297 8189 0 0
T10 3340 3301 0 0
T28 17224 17117 0 0
T29 1310 1285 0 0
T30 3476 3382 0 0
T31 4952 4859 0 0
T32 3309 3270 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 489171267 487131151 0 0
T5 180217 180123 0 0
T6 61931 61865 0 0
T8 1805 1726 0 0
T9 8297 8189 0 0
T10 3340 3301 0 0
T28 17224 17117 0 0
T29 1310 1285 0 0
T30 3476 3382 0 0
T31 4952 4859 0 0
T32 3309 3270 0 0

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 243852619 243852619 0 0
gen_no_flops.OutputDelay_A 243852619 243852619 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 243852619 243852619 0 0
T5 90062 90062 0 0
T6 30933 30933 0 0
T8 863 863 0 0
T9 4970 4970 0 0
T10 1811 1811 0 0
T28 8613 8613 0 0
T29 643 643 0 0
T30 1836 1836 0 0
T31 2569 2569 0 0
T32 1635 1635 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 243852619 243852619 0 0
T5 90062 90062 0 0
T6 30933 30933 0 0
T8 863 863 0 0
T9 4970 4970 0 0
T10 1811 1811 0 0
T28 8613 8613 0 0
T29 643 643 0 0
T30 1836 1836 0 0
T31 2569 2569 0 0
T32 1635 1635 0 0

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 121925673 121925673 0 0
gen_no_flops.OutputDelay_A 121925673 121925673 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 121925673 121925673 0 0
T5 45031 45031 0 0
T6 15466 15466 0 0
T8 432 432 0 0
T9 2483 2483 0 0
T10 904 904 0 0
T28 4306 4306 0 0
T29 321 321 0 0
T30 917 917 0 0
T31 1284 1284 0 0
T32 818 818 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 121925673 121925673 0 0
T5 45031 45031 0 0
T6 15466 15466 0 0
T8 432 432 0 0
T9 2483 2483 0 0
T10 904 904 0 0
T28 4306 4306 0 0
T29 321 321 0 0
T30 917 917 0 0
T31 1284 1284 0 0
T32 818 818 0 0

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 250871035 249836634 0 0
gen_no_flops.OutputDelay_A 250871035 249836634 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 250871035 249836634 0 0
T5 90112 90065 0 0
T6 30967 30934 0 0
T8 902 862 0 0
T9 4149 4095 0 0
T10 1670 1651 0 0
T28 8612 8559 0 0
T29 655 643 0 0
T30 1737 1691 0 0
T31 2476 2430 0 0
T32 1564 1545 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 250871035 249836634 0 0
T5 90112 90065 0 0
T6 30967 30934 0 0
T8 902 862 0 0
T9 4149 4095 0 0
T10 1670 1651 0 0
T28 8612 8559 0 0
T29 655 643 0 0
T30 1737 1691 0 0
T31 2476 2430 0 0
T32 1564 1545 0 0

Line Coverage for Instance : tb.dut.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 6 6


Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 168277061 166094603 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166094603 0 2415
T5 182105 181911 0 3
T6 10321 10296 0 3
T8 1862 1664 0 3
T9 2334 2285 0 3
T10 1878 1831 0 3
T28 1076 1061 0 3
T29 1338 1239 0 3
T30 3620 3377 0 3
T31 1289 1233 0 3
T32 871 845 0 3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 168277061 166094603 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166094603 0 2415
T5 182105 181911 0 3
T6 10321 10296 0 3
T8 1862 1664 0 3
T9 2334 2285 0 3
T10 1878 1831 0 3
T28 1076 1061 0 3
T29 1338 1239 0 3
T30 3620 3377 0 3
T31 1289 1233 0 3
T32 871 845 0 3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 168277061 166094603 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166094603 0 2415
T5 182105 181911 0 3
T6 10321 10296 0 3
T8 1862 1664 0 3
T9 2334 2285 0 3
T10 1878 1831 0 3
T28 1076 1061 0 3
T29 1338 1239 0 3
T30 3620 3377 0 3
T31 1289 1233 0 3
T32 871 845 0 3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 168277061 166094603 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166094603 0 2415
T5 182105 181911 0 3
T6 10321 10296 0 3
T8 1862 1664 0 3
T9 2334 2285 0 3
T10 1878 1831 0 3
T28 1076 1061 0 3
T29 1338 1239 0 3
T30 3620 3377 0 3
T31 1289 1233 0 3
T32 871 845 0 3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 168277061 166094603 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166094603 0 2415
T5 182105 181911 0 3
T6 10321 10296 0 3
T8 1862 1664 0 3
T9 2334 2285 0 3
T10 1878 1831 0 3
T28 1076 1061 0 3
T29 1338 1239 0 3
T30 3620 3377 0 3
T31 1289 1233 0 3
T32 871 845 0 3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 168277061 166094603 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166094603 0 2415
T5 182105 181911 0 3
T6 10321 10296 0 3
T8 1862 1664 0 3
T9 2334 2285 0 3
T10 1878 1831 0 3
T28 1076 1061 0 3
T29 1338 1239 0 3
T30 3620 3377 0 3
T31 1289 1233 0 3
T32 871 845 0 3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_no_flops.OutputDelay_A 168277061 166101610 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_no_flops.OutputDelay_A 168277061 166101610 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_no_flops.OutputDelay_A 168277061 166101610 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 168277061 166101610 0 0
gen_no_flops.OutputDelay_A 168277061 166101610 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168277061 166101610 0 0
T5 182105 181914 0 0
T6 10321 10299 0 0
T8 1862 1667 0 0
T9 2334 2288 0 0
T10 1878 1834 0 0
T28 1076 1064 0 0
T29 1338 1242 0 0
T30 3620 3380 0 0
T31 1289 1236 0 0
T32 871 848 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 518271421 0 0
gen_flops.gen_stable_chks.OutputDelay_A 522561045 518264489 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 522561045 34798 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518264489 0 2415
T5 187732 187532 0 3
T6 64514 64371 0 3
T8 1881 1680 0 3
T9 8643 8471 0 3
T10 3479 3393 0 3
T28 17942 17742 0 3
T29 1365 1265 0 3
T30 3620 3377 0 3
T31 5159 4945 0 3
T32 3385 3284 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 34798 0 0
T5 187732 1 0 0
T6 64514 1 0 0
T8 1881 10 0 0
T9 8643 17 0 0
T10 3479 17 0 0
T28 17942 5 0 0
T29 1365 11 0 0
T30 3620 23 0 0
T31 5159 13 0 0
T32 3385 17 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 518271421 0 0
gen_no_flops.OutputDelay_A 522561045 518271421 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 518271421 0 0
gen_flops.gen_stable_chks.OutputDelay_A 522561045 518264489 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 522561045 34753 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518264489 0 2415
T5 187732 187532 0 3
T6 64514 64371 0 3
T8 1881 1680 0 3
T9 8643 8471 0 3
T10 3479 3393 0 3
T28 17942 17742 0 3
T29 1365 1265 0 3
T30 3620 3377 0 3
T31 5159 4945 0 3
T32 3385 3284 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 34753 0 0
T5 187732 1 0 0
T6 64514 1 0 0
T8 1881 14 0 0
T9 8643 15 0 0
T10 3479 21 0 0
T28 17942 5 0 0
T29 1365 15 0 0
T30 3620 27 0 0
T31 5159 7 0 0
T32 3385 9 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 518271421 0 0
gen_no_flops.OutputDelay_A 522561045 518271421 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 518271421 0 0
gen_flops.gen_stable_chks.OutputDelay_A 522561045 518264489 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 522561045 34961 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518264489 0 2415
T5 187732 187532 0 3
T6 64514 64371 0 3
T8 1881 1680 0 3
T9 8643 8471 0 3
T10 3479 3393 0 3
T28 17942 17742 0 3
T29 1365 1265 0 3
T30 3620 3377 0 3
T31 5159 4945 0 3
T32 3385 3284 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 34961 0 0
T5 187732 1 0 0
T6 64514 1 0 0
T8 1881 14 0 0
T9 8643 21 0 0
T10 3479 25 0 0
T28 17942 9 0 0
T29 1365 13 0 0
T30 3620 23 0 0
T31 5159 11 0 0
T32 3385 9 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 518271421 0 0
gen_no_flops.OutputDelay_A 522561045 518271421 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
ALWAYS11711100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 4 4
117 1 1
168 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------
-1-StatusTests
0CoveredT8,T9,T10
1CoveredT8,T9,T10

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00
TERNARY 96 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


LineNo. Expression -1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T8,T9,T10


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 518271421 0 0
gen_flops.gen_stable_chks.OutputDelay_A 522561045 518264489 0 2415
gen_flops.gen_stable_chks.OutputIfUnstable_A 522561045 34924 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

gen_flops.gen_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518264489 0 2415
T5 187732 187532 0 3
T6 64514 64371 0 3
T8 1881 1680 0 3
T9 8643 8471 0 3
T10 3479 3393 0 3
T28 17942 17742 0 3
T29 1365 1265 0 3
T30 3620 3377 0 3
T31 5159 4945 0 3
T32 3385 3284 0 3

gen_flops.gen_stable_chks.OutputIfUnstable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 34924 0 0
T5 187732 1 0 0
T6 64514 1 0 0
T8 1881 18 0 0
T9 8643 21 0 0
T10 3479 15 0 0
T28 17942 3 0 0
T29 1365 5 0 0
T30 3620 29 0 0
T31 5159 11 0 0
T32 3385 13 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 522561045 518271421 0 0
gen_no_flops.OutputDelay_A 522561045 518271421 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 522561045 518271421 0 0
T5 187732 187535 0 0
T6 64514 64374 0 0
T8 1881 1683 0 0
T9 8643 8474 0 0
T10 3479 3396 0 0
T28 17942 17745 0 0
T29 1365 1268 0 0
T30 3620 3380 0 0
T31 5159 4948 0 0
T32 3385 3287 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%