Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T10
0	1	Unreachable
1	0	Covered	T4,T1,T20

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	168277061	165955916	0	0
AllClkBypReqTrue_A	168277061	143412	0	0
IoClkBypReqFalse_A	168277061	165877153	0	2415
IoClkBypReqTrue_A	168277061	217611	0	0
LcClkBypAckFalse_A	168277061	165969750	0	0
LcClkBypAckTrue_A	168277061	129578	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	165955916	0	0
T5	182105	181913	0	0
T6	10321	10298	0	0
T8	1862	1666	0	0
T9	2334	1905	0	0
T10	1878	1766	0	0
T28	1076	1063	0	0
T29	1338	1241	0	0
T30	3620	3279	0	0
T31	1289	1197	0	0
T32	871	847	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	143412	0	0
T1	0	1269	0	0
T5	182105	0	0	0
T6	10321	0	0	0
T9	2334	382	0	0
T10	1878	67	0	0
T13	0	514	0	0
T23	0	202	0	0
T26	0	4	0	0
T27	0	223	0	0
T28	1076	0	0	0
T29	1338	0	0	0
T30	3620	100	0	0
T31	1289	38	0	0
T32	871	0	0	0
T36	2673	289	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	165877153	0	2415
T5	182105	181911	0	3
T6	10321	10296	0	3
T8	1862	1664	0	3
T9	2334	1742	0	3
T10	1878	1744	0	3
T28	1076	983	0	3
T29	1338	1239	0	3
T30	3620	3050	0	3
T31	1289	1077	0	3
T32	871	845	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	217611	0	0
T1	0	2165	0	0
T5	182105	0	0	0
T6	10321	0	0	0
T9	2334	543	0	0
T10	1878	87	0	0
T23	0	52	0	0
T26	0	31	0	0
T27	0	353	0	0
T28	1076	78	0	0
T29	1338	0	0	0
T30	3620	327	0	0
T31	1289	156	0	0
T32	871	0	0	0
T36	2673	589	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	165969750	0	0
T5	182105	181913	0	0
T6	10321	10298	0	0
T8	1862	1666	0	0
T9	2334	1894	0	0
T10	1878	1757	0	0
T28	1076	1061	0	0
T29	1338	1241	0	0
T30	3620	3176	0	0
T31	1289	1175	0	0
T32	871	847	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168277061	129578	0	0
T1	0	1207	0	0
T5	182105	0	0	0
T6	10321	0	0	0
T9	2334	393	0	0
T10	1878	76	0	0
T23	0	49	0	0
T27	0	293	0	0
T28	1076	2	0	0
T29	1338	0	0	0
T30	3620	203	0	0
T31	1289	60	0	0
T32	871	0	0	0
T36	2673	336	0	0
T119	0	178	0	0