Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2090245932	16692	0	0
TransStop_A	2090245932	8609	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090245932	16692	0	0
T1	701232	294	0	0
T2	222788	0	0	0
T4	296764	0	0	0
T14	0	130	0	0
T20	508192	0	0	0
T21	10976	0	0	0
T22	13680	0	0	0
T23	10020	0	0	0
T24	0	4	0	0
T27	0	34	0	0
T38	221740	0	0	0
T40	37432	33	0	0
T47	15812	2	0	0
T89	0	5	0	0
T120	0	21	0	0
T121	0	4	0	0
T122	0	18	0	0
T123	0	114	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2090245932	8609	0	0
T1	701232	135	0	0
T2	222788	0	0	0
T4	296764	0	0	0
T14	0	66	0	0
T20	508192	0	0	0
T21	10976	0	0	0
T22	13680	0	0	0
T23	10020	0	0	0
T24	0	4	0	0
T27	0	17	0	0
T38	221740	0	0	0
T40	37432	19	0	0
T47	15812	2	0	0
T91	0	16	0	0
T120	0	12	0	0
T121	0	4	0	0
T122	0	13	0	0
T123	0	42	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	522561483	4206	0	0
TransStop_A	522561483	2117	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561483	4206	0	0
T1	175308	66	0	0
T2	55697	0	0	0
T4	74191	0	0	0
T14	0	32	0	0
T20	127048	0	0	0
T21	2744	0	0	0
T22	3420	0	0	0
T23	2505	0	0	0
T24	0	1	0	0
T27	0	9	0	0
T38	55435	0	0	0
T40	9358	8	0	0
T47	3953	1	0	0
T120	0	6	0	0
T121	0	1	0	0
T122	0	6	0	0
T123	0	26	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561483	2117	0	0
T1	175308	32	0	0
T2	55697	0	0	0
T4	74191	0	0	0
T14	0	14	0	0
T20	127048	0	0	0
T21	2744	0	0	0
T22	3420	0	0	0
T23	2505	0	0	0
T24	0	1	0	0
T27	0	4	0	0
T38	55435	0	0	0
T40	9358	3	0	0
T47	3953	1	0	0
T120	0	4	0	0
T121	0	1	0	0
T122	0	4	0	0
T123	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	522561483	4142	0	0
TransStop_A	522561483	2147	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561483	4142	0	0
T1	175308	77	0	0
T2	55697	0	0	0
T4	74191	0	0	0
T14	0	29	0	0
T20	127048	0	0	0
T21	2744	0	0	0
T22	3420	0	0	0
T23	2505	0	0	0
T24	0	1	0	0
T27	0	8	0	0
T38	55435	0	0	0
T40	9358	9	0	0
T47	3953	0	0	0
T89	0	3	0	0
T120	0	3	0	0
T121	0	1	0	0
T122	0	4	0	0
T123	0	32	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561483	2147	0	0
T1	175308	37	0	0
T2	55697	0	0	0
T4	74191	0	0	0
T14	0	15	0	0
T20	127048	0	0	0
T21	2744	0	0	0
T22	3420	0	0	0
T23	2505	0	0	0
T24	0	1	0	0
T27	0	5	0	0
T38	55435	0	0	0
T40	9358	5	0	0
T47	3953	0	0	0
T91	0	9	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	3	0	0
T123	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	522561483	4160	0	0
TransStop_A	522561483	2148	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561483	4160	0	0
T1	175308	75	0	0
T2	55697	0	0	0
T4	74191	0	0	0
T14	0	35	0	0
T20	127048	0	0	0
T21	2744	0	0	0
T22	3420	0	0	0
T23	2505	0	0	0
T24	0	1	0	0
T27	0	7	0	0
T38	55435	0	0	0
T40	9358	8	0	0
T47	3953	0	0	0
T89	0	2	0	0
T120	0	5	0	0
T121	0	1	0	0
T122	0	4	0	0
T123	0	26	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561483	2148	0	0
T1	175308	33	0	0
T2	55697	0	0	0
T4	74191	0	0	0
T14	0	18	0	0
T20	127048	0	0	0
T21	2744	0	0	0
T22	3420	0	0	0
T23	2505	0	0	0
T24	0	1	0	0
T27	0	3	0	0
T38	55435	0	0	0
T40	9358	5	0	0
T47	3953	0	0	0
T91	0	7	0	0
T120	0	3	0	0
T121	0	1	0	0
T122	0	2	0	0
T123	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	522561483	4184	0	0
TransStop_A	522561483	2197	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561483	4184	0	0
T1	175308	76	0	0
T2	55697	0	0	0
T4	74191	0	0	0
T14	0	34	0	0
T20	127048	0	0	0
T21	2744	0	0	0
T22	3420	0	0	0
T23	2505	0	0	0
T24	0	1	0	0
T27	0	10	0	0
T38	55435	0	0	0
T40	9358	8	0	0
T47	3953	1	0	0
T120	0	7	0	0
T121	0	1	0	0
T122	0	4	0	0
T123	0	30	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522561483	2197	0	0
T1	175308	33	0	0
T2	55697	0	0	0
T4	74191	0	0	0
T14	0	19	0	0
T20	127048	0	0	0
T21	2744	0	0	0
T22	3420	0	0	0
T23	2505	0	0	0
T24	0	1	0	0
T27	0	5	0	0
T38	55435	0	0	0
T40	9358	6	0	0
T47	3953	1	0	0
T120	0	4	0	0
T121	0	1	0	0
T122	0	4	0	0
T123	0	13	0	0